MT89L86 Data Sheet
19
Zarlink Semiconductor Inc.
Figure 5 - Connection Memory High (CMH) Bits
x=Don’t care
Connection Memory Low - Read/Write
Figure 6 - Connection Memory Low (CML) Bits
2 MC Message Channel. When 1, the contents of the corresponding location in Connection
Memory Low are output on the corresponding channel and stream. When 0, the contents
of the programmed location in Connection Memory Low act as an address for the Data
Memory and so determine the source of the connection to the location’s channel and
stream.
1 CSTo CSTo Bit. This bit is only available in 2.048 Mb/s applications. It drives a bit time on the
CSTo output pin.
0 OE Output Enable. This bit enables the output drivers on a per-channel basis. This allows
individual channels on individual streams to be made high-impedance, allowing switch
matrices to be constructed. A HIGH enables the driver and a LOW disables it.
Bit Name Description
7-5 SAB2-0* Source Stream Address bits. These three bits are used together with SAB3 in CMH to
select up to 16 different source streams for the connection. Depending on the switching
configuration and the data rate selected in the application, 1, 2, 3 or all 4 SAB bits can be
used. See Tables 9 and 10 for details.
4-0 CAB4-0* Source Channel Address bits 0-4. These five bits are used together with CAB5-6 in
CMH to select up 128 different source channels for the connection. Depending on the
switching configuration and the data rate used in the application, 5, 6 or all 7 CAB bits
can be used to select respectively 32, 64 or 128 different channels.
See Tables 9 and 10 for details.
If bit two (MC) of the corresponding Connection High locations is 1, or if bit 6 of the Control Register is 1, then these entire eight bits are output
on the corresponding output channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source
of the connection which is output on the channel and stream associated with this location.
Bit Name Description
XV/C SAB3 CAB6 CAB5 MC CSTo OE
76543210
(CM high bits)
SAB2 SAB1 SAB0 CAB4 CAB3 CAB2 CAB1 CAB0
76543210
(CM low bits)
MT89L86 Data Sheet
20
Zarlink Semiconductor Inc.
Table 9 - CAB and SAB Bits Programming for Identical I/O Rate Applications
Table 10 - CAB and SAB Bits Programming for Different I/O Rate Applications
Stream Pair Selection Register - Read/Write
Identical
I/O
Rate
# of Input x
Output
Streams
CAB bits used to determine the source
channel for the connection
SAB bits used to
determine the source
stream for the connection
2 Mb/s 8x8 CAB4 to CAB0 (32 channel/stream) SAB2, SAB1, SAB0
2 Mb/s 4x4 CAB4 to CAB0 (32 channel/stream) SAB2, SAB1
2 Mb/s 16x8 CAB4 to CAB0 (32 channel/stream) SAB3, SAB2, SAB1, SAB0
4 Mb/s 4x4 CAB5 to CAB0 (64 channel/stream) SAB2, SAB1
4 Mb/s 8x4 CAB5 to CAB0 (64 channel/stream) SAB2, SAB1, SAB0
8 Mb/s 2x2 CAB6 to CAB0 (128 channel/stream) SAB2
Nibble Switch
(2 Mb/s)
8x4 CAB5 to CAB0 (64 nibble/stream) SAB2, SAB1, SAB0
Different
I/O
Rate
# of Input x
Output Streams
CAB bits used to determine the source
channel for the connection
SAB bits used to
determine the source
stream for the
connection
2 Mb/s to 4 Mb/s 8x4 CAB4 to CAB0 (32 channel/stream) SAB2, SAB1, SAB0
2 Mb/s to 8 Mb/s 8x2 CAB4 to CAB0 (32 channel/stream) SAB2, SAB1, SAB0
4 Mb/s to 2 Mb/s 4x8 CAB5 to CAB0 (64 channel/stream) SAB2, SAB1
8 Mb/s to 2 Mb/s 2x8 CAB6 to CAB0 (128 channel/stream) SAB2
Bit Name Description
5-3 SPA2-0 Stream Pair A selection. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPA2
SPA1 SPA0 Stream Pair A Connected
0 0 0 STi2 / STo2
0 0 1 STi3 / STo3
0 1 0 STi4 / STo4
0 1 1 STi5 / STo5
1 0 0 STi6 / STo6
1 0 1 STi7 / STo7
1 1 0 STi8 / STo8
1 1 1 STi9 / STo9
X X SPA2 SPA1 SPA0 SPB2 SPB1 SPB0
76543210
MT89L86 Data Sheet
21
Zarlink Semiconductor Inc.
Figure 7 - Stream Pair Selection (SPS) Register
x=Don’t care
Frame Input Offset Register - Read/Write
Figure 8 - Frame Input Offset (FIO) Register
2-0 SPB2-0 Stream Pair B selection. These three bits define which pair of streams are going to be
connected to the switch matrix, together with the permanently connected streams
STi0-1 / STo0-1.
SPB2
SPB1 SPB0 Stream Pair B Connected
0 0 0 STi2 / STo2
0 0 1 STi3 / STo3
0 1 0 STi4 / STo4
0 1 1 STi5 / STo5
1 0 0 STi6 / STo6
1 0 1 STi7 / STo7
1 1 0 STi8 / STo8
1 1 1 STi9 / STo9
These bits are only used when the Switching Configuration bits enable stream pair selection capability (SCB 1-0 =10) and the Input Data Rate
Selection bits enable 2 Mb/s operation (IDR-0 = 00). In all other modes, the contents of this register are ignored.
Bit Name Description
7-5 OFB2-0 Offset Bits 2-0. These three bits define the time it takes the Serial Interface receiver to
recognize and store the first bit of the serial input streams; i.e., to start assuming a new
internal frame. The input frame offset can be selected to be up to 4 CK clock periods from
the time when frame pulse input signal is applied to the FR input.
OFB2
OFB1 OFB0 Number of Clock Periods
0 0 0 Normal Operation. No bit offsetting.
00 1 1
01 0 2
01 1 3
10 0 4
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
If frame input offset operation is not required, this register should be cleared by the CPU during system initialization.
Bit Name Description
X X SPA2 SPA1 SPA0 SPB2 SPB1 SPB0
76543210
OFB2 OFB1 OFB0 X X X X X
76543210

MT89L86APR1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Digital Bus Switch ICs Pb Free LOW VOLTAGE MULTIRATE DIGITL SW
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet