2. Value calculated reflects all module ranks in this operating condition.
Table 12: DDR2 I
DD
Specifications and Conditions – 2GB (Die Revision M)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol -1GA
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD0
1
680 600 560 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL =
CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
DD4W
I
DD1
1
760 680 640 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
I
DD2P
2
160 160 160 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-
puts are floating
I
DD2Q
2
448 384 384 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH,
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
I
DD2N
2
544 448 384 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address
bus inputs are stable; Data bus inputs are floating
Fast PDN exit MR[12] = 0 I
DD3P
2
512 480 448 mA
Slow PDN exit MR[12] = 1 320 320 320
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Oth-
er control and address bus inputs are switching; Data bus inputs are switching
I
DD3N
2
640 528 480 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
I
DD4W
1
1240 1080 1000 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data bus inputs are switching
I
DD4R
1
1200 1040 960 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) in-
terval; CKE is HIGH, S# is HIGH between valid commands; Other control and ad-
dress bus inputs are switching; Data bus inputs are switching
I
DD5
2
1400 1320 1280 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
I
DD6
2
112 112 112 mA
1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
IDD Specifications
PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
13
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