Table 15: SPD EEPROM AC Operating Conditions (Continued)
Parameter/Condition Symbol Min Max Units Notes
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F – 300 ns 2
SDA and SCL rise time
t
R – 300 ns 2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I – 50 ns
Clock LOW period
t
LOW 1.3 – µs
SCL clock frequency
t
SCL – 400 kHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.
1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. D 4/14 EN
16
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