©2015 Integrated Device Technology, Inc.
OCTOBER 2015
DSC-3026/12
1
HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH
INTERRUPTS
IDT71V321S/L
Features
High-speed access
Commercial & Industrial: 25/35/55ns (max.)
Low-power operation
IDT71V321S
Active: 325mW (typ.)
Standby: 5mW (typ.)
IDT71V321L
Active: 325mW (typ.)
Standby: 1mW (typ.)
Two INT flags for port-to-port communications
Functional Block Diagram
NOTES:
1. IDT71V321 (MASTER): BUSY is an output
2. BUSY and INT are totem-pole outputs.
On-chip port arbitration logic (IDT71V321 only)
BUSY output flag
Fully asynchronous operation from either port
Battery backup operation—2V data retention (L only)
TTL-compatible, single 3.3V power supply
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
3026 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/W
L
INT
L
BUSY
R
I/O
0R
-I/O
7R
A
10R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
11
11
R/W
R
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
IDT71V321J
J52
(4)
52-Pin PLCC
Top View
(5)
INDEX
I/O
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
3L
2L
OE
R
A
A
A
A
A
A
A
A
A
A
NC
I/O
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
4
L
5
L
6
L
7
L
N
C
G
N
D
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
0
R
1
R
2
R
3
R
4
R
6
R
5
R
A
0
L
O
E
L
A
1
0
L
I
N
T
L
B
U
S
Y
L
R
/
W
L
C
E
L
V
C
C
C
E
R
R
/
W
R
B
U
S
Y
R
I
N
T
R
A
1
0
R
1
234567474849505152
9
8
10
11
12
13
14
15
16
17
18
19
20
27262524232221 333231302928
35
34
36
37
38
39
40
41
42
43
44
45
46
3026 drw 02
Pin Configurations
(1,2,3)
Description
The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with
internal interrupt logic for interprocessor communications. The
IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port
RAM.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 325mW of power. Low-power (L) ver-
sions offer battery backup data retention capability, with each Dual-Port
typically consuming 200µW from a 2V battery.
The IDT71V321 devices are packaged in a 52-pin PLCC, a 64-pin
TQFP (thin quad flatpack), and a 64-pin STQFP (super thin quad
flatpack).
INDEX
IDT71V321PF or TF
PP64
(4)
&
PN64
(4)
64-Pin STQFP
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
6
4
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
G
N
D
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
3
R
I
/
O
4
R
I
/
O
5
R
I
/
O
3
L
N
/
C
N
/
C
G
N
D
N
/
C
N
/
C
A
1
0
R
V
C
C
B
U
S
Y
L
R
/
W
L
C
E
R
R
/
W
R
B
U
S
Y
R
C
E
L
N
/
C
N
/
C
A
1
0
L
V
C
C
N
/
C
I
N
T
R
I
N
T
L
3026 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
2. VTERM must not exceed Vcc + 0.3V.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Symbol Rating Commercial
& Industrial
Unit
V
TERM
(2 )
Te rminal Vo ltage
with Respect
to GND
-0.5 to +4.6 V
T
A
Operating
Temperature
0 to +70 °C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50 mA
3026 tbl 01
Grade Ambient
Temperature
GND Vcc
Commercial 0
O
C to +70
O
C0V3.3V
+
0.3V
Industrial -40
O
C to +85
O
C0V 3.3V
+
0.3V
3026 tbl 02
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 3.0 3.3 3.6 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
CC
+0.3
(2)
V
V
IL
Input Low Voltage -0.3
(1)
____
0.8 V
3026 tbl 03
Capacitance
(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol Parameter Conditions
(2 )
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Output Capacitance V
OUT
= 3dV 10 pF
3026 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
Symbol Parameter Test Conditions
71V321S 71V321L
UnitMin. Max. Min. Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.6V,
V
IN
= 0V to V
CC
___
10
___
A
|I
LO
| Output Leakage Current CE = V
IH
, V
OUT
= 0V to V
CC
V
CC
= 3.6V
___
10
___
A
V
OL
Output Low Voltage I
OL
= 4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
3026 tbl 05
NOTE:
1. At VCC < 2.0V input leakages are undefined.

71V321S55J8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2Kx8 ASYNCHRONOUS 3.3V DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
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