6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,2)
(VCC = 3.3V ± 0.3V)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Symbol Parameter Test Condition Version
71V321X25
Com'l & Ind
71V321X35
Com'l & Ind
71V321X55
Com'l & Ind
Unit
Typ.
Max. Typ. Max. Typ. Max.
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L S
L
55
55
130
100
55
55
125
95
55
55
115
85
mA
IND L 55 130 55 125 55 115
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
R
= CE
L
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3)
COM'L S
L
15
15
35
20
15
15
35
20
15
15
35
20
mA
IND L 15 35 15 35 15 35
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
= SEM
L
= V
IH
COM'L S
L
25
25
75
55
25
25
70
50
25
25
60
40
mA
IND L 25 75 25 70 25 60
I
SB3
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L
1.0
0.2
5
3
1.0
0.2
5
3
1.0
0.2
5
3
mA
IND L 0.2 6 1.0 5 1.0 5
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L S
L
25
25
70
55
25
25
65
50
25
25
55
40
mA
IND L 25 70 25 65 25 55
3026 tbl 06
Data Retention Characteristics (L Version Only)
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
for Data Retention 2.0
___
0V
I
CCDR
Data Retention Current
V
CC
= 2
V,
CE > V
CC
- 0.2V COM'L.
___
100 500
µA
t
CDR
(3)
Chip Deselect to Data
Retention Time
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V IND.
___
100 1000 µA
0
___ ___
V
t
R
(3)
Operation Recovery Time t
RC
(2)
___ ___
V
3026 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
Data Retention Waveform
V
CC
CE
3.0V 3.0V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
3026 drw 04
,
AC Test Conditions
590
30pF
435
DATA
OUT
590
435
5pF
DATA
OUT
3026 drw 05
3.3V
3.3V
BUSY
INT
,
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
3026 tbl 08
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(2)
71V321X25
Com'l & Ind
71V321X35
Com'l & Ind
71V321X55
Com'l & Ind
UnitSymbol Parameter Min. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 25
____
35
____
55
____
ns
t
AA
Address Access Time
____
25
____
35
____
55 ns
t
ACE
Chip Enable Access Time
____
25
____
35
____
55 ns
t
AOE
Output Enable Access Time
____
12
____
20
____
25 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
30 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
____
50 ns
3026 tbl 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
6
CE
t
ACE
t
HZ
t
LZ
t
PD
VALID DATA
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
3026 drw 07
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
t
AOE
t
PU
Timing Waveform of Read Cycle No. 2, Either Side
(3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 1, Either Side
(1)
NOTES:
1. R/W = V
IH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
3026 drw 06
t
BDD
(2,3)
BUSY
OUT

71V321S55J8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 2Kx8 ASYNCHRONOUS 3.3V DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union