6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation.
Depth Expansion
The BUSY arbitration, is based on the chip enable and address
signals only. It ignores whether an access is a read or write.
The BUSY outputs on the IDT71V321 are totem-pole type outputs and
do not require pull-up resistors to operate. If these RAMs are being
expanded in depth, then the BUSY indication for the resulting array
requires the use of an external AND gate
Functional Description
The IDT7V1321 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT71V321 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire memory
array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
3026 drw 16
D
E
C
O
D
E
R
BUSY
R
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
Figure 3. Busy and chip enable routing for depth
expansion with IDT71V321.
