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71V321S55J8

P1-P3P4-P6P7-P9P10-P12P13-P15
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
10
Timing Waveform of BUSY Arbitration Controlled by CE Timing
(1)
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
NOTES:
1. t
WH must be met for BUSY output 71V321.
2. BUSY is asserted on port 'B' blocking R/W
'B', until BUSY'B' goes HIGH.
3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY
(3)
BUSY
"B"
3026 drw 11
R/W
"A"
t
WP
t
WH
R/W
"B"
(2)
(1)
,
t
APS
(2)
ADDR
"A" AND "B"
ADDRESSES MATCH
t
BAC
t
BDC
CE
"B"
CE
"A"
BUSY
"A"
3026 drw 12
BUSY
"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
ADDR
"A"
ADDR
"B"
t
RC OR
t
WC
3026 drw 13
(2)
t
BAA
t
BDA
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
71V321X25
Com'l & Ind
71V321X35
Com'l & Ind
71V321X55
Com'l & Ind
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Interrupt Set Time
____
25
____
25
____
45 ns
t
INR
Interrupt Reset Time
____
25
____
25
____
45 ns
3026 tbl 12
Timing Waveform of Interrupt Mode
(1)
SET INT
CLEAR INT
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
t
INS
ADDR
"A"
INT
"B"
INTERRUPT ADDRESS
t
WC
t
AS
R/W
"A"
t
WR
3026 drw 14
(3)
(3)
(2)
(4)
t
RC
INTERRUPT CLEAR ADDRESS
ADDR
"B"
OE
"B"
t
INR
INT
"B"
3026 drw 15
t
AS
(3)
(3)
(2)
,
6.42
IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
12
Table III — Address BUSY Arbitration
Table I
—
Non-Contention
Read/Write Control
(4)
NOTES:
1. Pins BUSYL and BUSYR are both outputs. BUSYX outputs on the IDT71V321 are totem-
pole.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this
port. 'H' if the inputs to the opposite port became stable after the address and enable inputs
of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
Truth Tables
Table II
—
Interrupt Flag
(1,4)
NOTES:
1. A
0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
WDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
10L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
10R
-A
0R
INT
R
LLX7FFXXXX X L
(2 )
Set Right INT
R
Flag
XXXXXXLL7FFH
(3)
Reset Right INT
R
Flag
XXX X L
(3)
LLX7FEXSet Left INT
L
Flag
XLL7FEH
(2)
X X X X X Reset Left INT
L
Flag
3026 tbl 14
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
10L
A
OR
-A
10R
BUSY
L
(1 )
BUSY
R
(1)
XXNO MATCH H H Normal
HX MATCH H H Normal
XH MATCH H H Normal
L L MATCH (2) (2) Write Inhibit
(3 )
3026 tbl 15
Left or Right Port
(1)
R/W
CE OE
D
0-7
Function
XHX Z
Port Deselected and in Power-
Down Mode. I
SB2
or I
SB4
XHX Z
CE
R
= CE
L
= V
IH,
Power-Down Mode I
SB1
or I
SB3
LLXDATA
IN
Data on Port Written Into Memory
(2)
HLLDATA
OUT
Data in Memory Output on Port
(3)
H L H Z High-impedance Outputs
3026 tbl 13
P1-P3P4-P6P7-P9P10-P12P13-P15

71V321S55J8

Mfr. #:
Buy 71V321S55J8
Manufacturer:
IDT
Description:
SRAM 2Kx8 ASYNCHRONOUS 3.3V DUAL-PORT RAM
Lifecycle:
New from this manufacturer.
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