28
LTC3819
3819f
APPLICATIO S I FOR ATIO
WUU
U
Figure 4 illustrates the RMS input current drawn from the
input capacitance vs the duty cycle as determined by the
ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 50%
in a 2-phase solution due to the current splitting between
the two stages.
An interesting result of the 2-phase solution is that the V
IN
which produces worst-case ripple current for the input
capacitor, V
OUT
= V
IN
/2, in the single phase design pro-
duces zero input current ripple in the 2-phase design.
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V
OUT
/L discharge current
term from the stage that has its bottom MOSFET on
subtracts current from the (V
IN
– V
OUT
)/L charging current
resulting from the stage which has its top MOSFET on. The
output ripple current is:
∆I
V
fL
DD
D
RIPPLE
OUT
=
−−
()
− +
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
2
12 1
12 1
where D is duty factor.
The input and output ripple frequency is increased by the
number of stages used, reducing the output capacity
requirements. When V
IN
is approximately equal to 2(V
OUT
)
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.
Figure 12 shows a typical application using LTC3819 to
power the SUN CPU core. The input can vary from 7V to
24V, the output voltage can be programmed from 1.025V
to 1.4125V with a maximum current of 42A. This power
supply receives three input signals to generate different
output voltage offsets based on the operation conditions.
