OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

VND5050JTR-E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
Electrical specifications VND5050J-E / VND5050K-E
10/37 Doc ID 12266 Rev 7
Table 9.
Protections
(1)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
DC short circuit current
V
CC
=13V
5V<V
CC
<36V
12 18 24
24
A
A
I
limL
Short circuit current
during thermal cycling
V
CC
=13V
T
R
<T
j
<T
TSD
7A
T
TSD
Shutdown temperature 150 175 200 °C
T
R
Reset temperature
T
RS
+ 1 T
RS
+ 5
°C
T
RS
Thermal reset of
STATUS
135 °C
T
HYST
Thermal hysteresis
(T
TSD
-T
R
)
7°C
t
SDL
Status delay in overload
conditions
T
j
>T
TSD
(see
Figure 4
)20µs
V
DEMAG
Turn-off output voltage
clamp
I
OUT
=2A; V
IN
=0; L=6mH
V
CC
-41 V
CC
-46 V
CC
-52
V
V
ON
Output voltage drop
limitation
I
OUT
= 0.1A;
T
j
= -40°C...+150°C
(see
Figure 6
)
25 mV
Table 10. Openload detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
OL
Openload on-state
detection threshold
V
IN
= 5V,8V<V
CC
<18V 10
See
Figure 19
70 mA
t
DOL(on)
Openload on-state
detection delay
I
OUT
= 0A, V
CC
=13V
(see Figure 4)
200 µs
t
POL
Delay between INPUT
falling edge and STATUS
rising edge in Openload
condition
I
OUT
= 0A (see
Figure 4
) 200 500 1000 µs
V
OL
Openload off-state
voltage detection
threshold
V
IN
= 0V, 8V<V
CC
<16V 2
See
Figure 20
4V
t
DSTKON
Output short circuit to
V
CC
detection delay at
turn-off
(see
Figure 4
)180t
POL
µs
VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 11/37
Figure 4. Status timings
Table 11. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level 0.9 V
I
IL
Low level input current V
IN
=0.9 V 1 µA
V
IH
Input high level 2.1 V
I
IH
High level input current V
IN
= 2.1 V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
STAT_DIS low level
voltage
0.9 V
I
SDL
Low level STAT_DIS
current
V
SD
= 0.9 V 1 µA
V
SDH
STAT_DIS high level
voltage
2.1 V
I
SDH
High level STAT_DIS
current
V
SD
= 2.1 V 10 µA
V
SD(hyst)
STAT_DIS hysteresis
voltage
0.25 V
V
SDCL
STAT_DIS clamp voltage
I
SD
= 1mA
I
SD
= -1mA
5.5
-0.7
7V
V
V
IN
V
STAT
t
POL
OPEN LOAD STATUS TIMING (without external pull-up)
I
OUT
< I
OL
V
OUT
< V
OL
t
DOL(on)
V
IN
V
STAT
OPEN LOAD STATUS TIMING (with external pull-up)
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
V
IN
V
STAT
OVER TEMP STATUS TIMING
t
SDL
t
SDL
T
j
> T
TSD
V
IN
V
STAT
t
DSTKON
OUTPUT STUCK TO V
CC
I
OUT
> I
OL
V
OUT
> V
OL
t
DOL(on)
Electrical specifications VND5050J-E / VND5050K-E
12/37 Doc ID 12266 Rev 7
Figure 5. Switching characteristics
Table 12. Truth table
Conditions Input Output Sense (V
CSD
=0V)
(1)
1. If the V
CSD
is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
Over temperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output voltage > V
OL
L
H
H
H
L
(2)
H
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
Output current < I
OL
L
H
L
H
H
(3)
L
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10%
t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37

VND5050JTR-E

Mfr. #:
Buy VND5050JTR-E
Manufacturer:
STMicroelectronics
Description:
Power Switch ICs - Power Distribution Double Ch Hi Side Driver auto
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet