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VND5050JTR-E
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P37
Package
and PCB th
ermal data
VND505
0J-E / VND505
0K-E
28/37
Doc ID 12266
Rev 7
Figure 37.
PowerSSO-24™ thermal impedance junction ambient single pulse (one
channel on)
Equation 2: pulse calculation formula
where
δ
= t
P
/T
Figure 38.
Thermal fitting model of a double channel HSD in PowerSSO-24™
(b)
b.
The fitting model is a
simplified thermal tool an
d is valid for
transient evolutions where the em
bedded
protections (power limitation or thermal cyc
ling during thermal shutdown)
are not triggered.
Z
TH
δ
R
TH
δ
Z
THtp
1
δ
–
()
+
⋅
=
VND505
0J-E / VN
D5050K-E
Packag
e and PCB th
ermal data
Doc ID 1
2266 Re
v 7
29/37
T
able 17.
PowerSSO
-24™ ther
mal parameters
Area/island (cm
2
)F
o
o
t
p
r
i
n
t
28
R1=R7 (°C/W)
0.4
R2=R8 (°C/W)
2
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W
.s/°C)
0.001
C2=C8 (W
.s/°C)
0.0022
C3 (W
.s/°C)
0.025
C4 (W
.s/°C)
0.75
C5 (W
.s/°C)
1
4
9
C6 (W
.s/°C)
2.2
5
17
Package
and packin
g informa
tion
VND505
0J-E / VND505
0K-E
30/37
Doc ID 12266
Rev 7
5
Package and packing information
5.1 ECOP
ACK
®
p
ackages
In orde
r to meet e
nvironm
ental requi
rements, ST offers th
ese de
vices
in different gr
ades of
ECOP
ACK
®
packages
, dependi
ng on th
eir level
of env
ironmental com
pliance
. ECOP
ACK
®
speci
fication
s, grade
definitio
ns and pr
oduct
status are a
vailable a
t:
www
.st.com
.
ECOP
ACK
®
is an
ST tra
demark.
5.2 PowerSSO
-12™
p
ackage i
nformation
Figure 39.
PowerSSO-12™ p
ackage dimensions
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P37
VND5050JTR-E
Mfr. #:
Buy VND5050JTR-E
Manufacturer:
STMicroelectronics
Description:
Power Switch ICs - Power Distribution Double Ch Hi Side Driver auto
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
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Products related to this Datasheet
VND5050JTR-E
VND5050J-E
VND5050KTR-E
VND5050K-E