ISL6142IBZA-T Datasheet ISL6142IBZA, ISL6142CBZA-T, ISL6142IBZA-T | P16-P18

C1 and R3 prevent Q1 from turning on momentarily when

power is first applied. Without them, C2 would pull the gate

of Q1 up to a voltage roughly equal to V

*C2/Cgs(Q1)

(where Cgs is the FET gate-source capacitance) before the

ISL6142/52 could power up and actively pull the gate low.

Place C1 in parallel with the gate capacitance of Q1; isolate

them from C2 by R3.

C1 =[(Vinmax - Vth)/Vth] * (C2+Cgd) - where Vth is the

FET’s minimum gate threshold, Vinmax is the maximum

operating input voltage, and Cgd is the FET gate-drain

capacitance.

R3 - its value is not critical, a typical value of 18k is

recommended but values down to 1K can be used. Lower

values of R3 will add delay to gate turn-on for hot insertion

and the single retry event following a hard fault.

R7/R8/R9 - are used to sense the load current (R7/R8) and

convert the scaled output current (IS

OUT

) to a voltage (R9)

that would typically be the input signal to an A to D converter.

R7 is connected between -IS and the R1 sense resistor.

These two resistors set the I

SENSE

(current through the

Rsense resistor) to IS

OUT

scaling factor based on equation 5

below. R8 does not effect the scaling factor but should match

R7 to minimize IS

OUT

error. Their tolerance should be +/-1%,

which will typically result in an output current error of less than

5% for a full scale condition. The trace layout is also critical to

obtain optimum performance. The traces connecting these

resistors to the device pins (IS+ and IS-) and to the R1 sense

resistor should be kept as short as possible, match in length,

and be isolated from the main current flow as illustrated in

figure 30.

R9 is used to convert the IS

OUT

current to voltage and is

connected between the IS

OUT

pin and -V

. The current

flowing through the resistor (EQ. 5) should not exceed 600A

and the voltage on the CT pin will clamp at approximately 8V.

To select the appropriate resistor values for the application

the user must first define the R1 sense resistor value and the

maximum load current to be detected/measured. The value

of R7 should then be selected such that the maximum IS

OUT

current is in the 400-500A range. For example, if the user

wanted to detect and measure fault currents up to the hard

fault comparator trip point (10A); the maximum IS

OUT

current using the application components in figure 23 would

be [10A x (.02/400] = 500A. The value of R9 should be set

to accommodate the dynamic range of the A to D converter.

For this example, a 5K resistor would produce a full scale

input voltage to the converter of 2.5V (500A x 5K).

Figures 32 and 33 illustrate the typical output voltage

response of the current sense circuit for the Over-Current

Time-out and hard fault single retry events.

R10 - is a pull-up resistor for the open drain FAULT

output

pin which goes active low when the Over-Current latch is set

(Over-Current Time-Out). The output signal is referenced to

and the resistor is connected to a positive voltage, 5V or

less, with respect to V

. A typical value of 5K is

recommended. A fault indicator LED can be placed in series

with the pull-up resistor if desired. The resistor value should

be selected such that it will allow enough current to drive the

LED adequately (brightness).

C3 - is the capacitor used to program the current limit time-

out period. When the Over-Current threshold is exceeded a

20A (nominal) current source will charge the C3 capacitor

from V

to approximately 8.5V. When the voltage on the CT

pin exceeds the 8.5V threshold, the GATE pin will

immediately be pulled low with a 70ma pull down device, the

Over-Current latch will be set, and the FET will be turned off.

If the Over-Current condition goes away before the time-out

period expires, the CT pin will be pulled back down to V

and normal operation will resume. Note that any parasitic

capacitance from the CT pin to -V

will effectively add to

C3. This additional capacitance should be taken into account

when calculating the C3 value needed for the desired time-

out period.

The value of C3 can be calculated using equation 6 where dt

is the time-out period, dv is the CT pin threshold, and I

the capacitor charging current.

Q2- is an N-channel logic FET used to drive the disable pin

(DIS). The DIS pin is used to enable/disable the external

pass transistor (Q1) by turning the GATE drive voltage on or

off. The DIS pin can also be used to reset the Over-Current

latch by toggling the pin high and then low. When Q2 is off,

the DIS pin is pulled high with an internal 500K resistor,

connected to an internal +5V (V

+ 5V) supply rail (10A).

In this condition the GATE pin is low, and Q1 is turned off.

When Q2 is on, the DIS pin is pulled low to V

allowing the

GATE pin to pull up and turn on Q1. The gate of Q2 will

typically be driven low (<1.5V) or High (>3.0V) with external

logic circuitry referenced to the negative input (-V

Low-side Application

Although this IC was designed for -48V systems, it can also

be used as a low-side switch for positive 48V systems; the

operation and components are usually similar. One possible

difference is the kind of level shifting that may be needed to

interface logic signals to the IC. For example, many of the IC

functions are referenced to the IC substrate, connected to the

pin, but this pin may be considered -48V or GND,

depending upon the polarity of the system. Also, the input or

output logic (running at 5V or 3.3V or even lower) might be

OUT

SENSE

-----------------------=

(EQ. 5)

------ I



timeout

8.5V

---------------------- 20

6–

10==

(EQ. 6

ISL6142, ISL6152

externally referenced to either V

or V

of the IC, instead

of GND.

Inrush Current Control

The primary function of the ISL6142/52 hot plug controller is

to control the inrush current. When a board is plugged into a

live backplane, the input capacitors of the board’s power

supply circuit can produce large current transients as they

charge up. This can cause glitches on the system power

supply (which can affect other boards!), as well as possibly

cause some permanent damage to the power supply.

The key to allowing boards to be inserted into a live backplane

is to turn on the power to the board in a controlled manner,

usually by limiting the current allowed to flow through a FET

switch, until the input capacitors are fully charged. At that

point, the FET is fully on, for the smallest voltage drop across

it. Figure 31 illustrates the typical inrush current response for a

hot insertion under the following conditions:

= -48V, Rsense = 0.02W

Current limit = 50mV / 0.02 = 2.5A

C1 = 150nF, C2 = 3.3nF, R3 = 18k

CL = 100F, RL = 50, I

LOAD

= 48V / 50 ~1.0A

inrush

= 50A (100F / 3.3nF) = 1.5A

After the contact bounce subsides the UVLO and UV criteria

are quickly met and the GATE begins to ramp up. As the

GATE reaches approximately 4V with respect to the source,

the FET begins to turn on allowing current to charge the

100F load capacitor. As the drain to source voltage begins to

drop, the feedback network of C2 and R3 hold the GATE

constant, in this case limiting the current to approximately

1.5A. When the DRAIN voltage completes its ramp down, the

load current remains constant at approximately 1.0A as the

GATE voltage increases to its final value.

Electronic Circuit Breaker/Current Limit

The ISL6142/52 allows the user to program both the current

limit and the time-out period to protect the system against

excessive supply or fault currents. The IntelliTrip

electronic

circuit breaker is capable of detecting both hard faults, and

less severe Over-Current conditions.

The Over-Current trip point is determined by R1 (EQ. 3) also

referred to as Rsense. When the voltage across this resistor

exceeds 50mV, the current limit regulator will turn on, and the

GATE will be pulled lower (to ~4V) to regulate current through

the FET at 50mV/Rsense. If the fault persists and current

limiting exceeds the programmed time-out period, the FET will

be turned off by discharging the GATE pin to V

. This will set

the Over-Current latch and the PWRGD

/PWRGD output will

transition to the inactive state, indicating power is no longer

good. To clear the latch and initiate a normal start-up

sequence, the user must either power down the system

(below the UVLO voltage), toggle the UV pin below and above

its threshold (usually with an external transistor), or toggle the

DIS pin high to low. Figure 32 shows the Over-Current shut

down and current limiting response for a 10 short to ground

on the output. Prior to the short circuit the output load is 110

producing an operating current of about 0.44A (48V/110). A

10 short is then applied to the output causing an initial fault

current of 4.8A. This produces a voltage drop across the

0.02 sense resistor of approximately 95mV, roughly two

times the Over-Current threshold of 50mV. The GATE is

quickly pulled low to limit the current to 2.5A (50mV/Rsense)

and the timer is enabled. The fault condition persists for the

duration of the programmed time-out period (C3 = 1500pF)

and the GATE is latched off in about 740s. There is a short

filter (3s nominal) on the comparator, so current transients

shorter than this will be ignored. Longer transients will initiate

the GATE pull down, current limiting, and the timer. If the fault

current goes away before the time-out period expires the

device will exit the current limiting mode and resume normal

operation.

In addition to current limiting and programmable time-out,

there is a hard fault comparator to respond to short circuits

with an immediate GATE shutdown (typically 10s) and a

single retry. The trip point of this comparator is set ~4 times

FIGURE 31. HOT INSERTION INRUSH CURRENT LIMITING,

DISABLE PIN TIED TO V

FIGURE 32. CURRENT LIMITING AND TIME-OUT

ISL6142, ISL6152

(210mV) higher than the Over-Current threshold of 50mV. If

the hard fault comparator trip point is exceeded, a hard pull

down current (350mA) is enabled to quickly pull down the

GATE and momentarily turn off the FET. The fast shutdown

resets the timer and is followed by a soft start, single retry

event. If the fault is still present after the GATE is slowly

turned on, the current limit regulator will trip (sense pin

voltage > 50mV), turn on the timer, and limit the current to

50mV/Rsense. If the fault remains and the time-out period is

exceeded the GATE pin will be latched low. Note: Since the

timer starts when the SENSE pin exceeds the 50mV

threshold, then depending on the speed of the current

transient exceeding 200mV; it’s possible that the current limit

time-out and shutdown can occur before the hard fault

comparator trips (and thus no retry). Figure 33 illustrates the

hard fault response with a zero ohm short circuit at the output.

As in the Over-Current Time-Out response discussed

previously, the supply is set at -48V and the current limit is

set at 2.5A. After the initial gate shutdown (10s) a soft start

is initiated with the short circuit still present. As the GATE

slowly turns on the current ramps up and exceeds the Over-

Current threshold (50mV) enabling the timer and current

limiting (2.5A). The fault remains for the duration of the time-

out period and the GATE pin is quickly pulled low and

latched off.

Applications: OV and UV

The UV and OV pins can be used to detect Over-Voltage

and Under-Voltage conditions on the input supply and

quickly shut down the external FET to protect the system.

Each pin is tied to an internal comparator with a nominal

reference of 1.255V. A resistor divider between the V

(gnd) and -V

is typically used to set the trip points on the

UV and OV pins. If the voltage on the UV pin is above its

threshold and the voltage on the OV pin is below its

threshold, the supply is within its expected operating range

and the GATE will be allowed to turn on, or remain on. If the

UV pin voltage drops below its high to low threshold, or the

OV pin voltage increases above its low to high threshold, the

GATE pin will be pulled low, turning off the FET until the

supply is back within tolerance.

The OV and UV inputs are high impedance, so the value of

the external resistor divider is not critical with respect to input

current. Therefore, the next consideration is total current; the

resistors will always draw current, equal to the supply

voltage divided by the total resistance of the divider

(R4+R5+R6) so the values should be chosen high enough to

get an acceptable current. However, to the extent that the

noise on the power supply can be transmitted to the pins, the

resistor values might be chosen to be lower. A filter capacitor

from UV to -V

or OV to -V

is a possibility, if certain

transients need to be filtered. (Note that even some

transients which could momentarily shut off the GATE might

recover fast enough such that the GATE or the output

current does not even see the interruption).

Finally, take into account whether the resistor values are

readily available, or need to be custom ordered. Tolerances

of 1% are recommended for accuracy. Note that for a typical

48V system (with a 43V to 72V range), the 43V or 72V is

being divided down to 1.255V, a significant scaling factor.

For UV, the ratio is roughly 35 times; every 3mV change on

the UV pin represents roughly 0.1V change of power supply

voltage. Conversely, an error of 3mV (due to the resistors,

for example) results in an error of 0.1V for the supply trip

point. The OV ratio is around 60. So the accuracy of the

resistors comes into play.

The hysteresis of the comparators is also multiplied by the

scale factor of 35 for the UV pin (35 * 135mV = 4.7V of

hysteresis at the power supply) and 60 for the OV pin (60 *

25mV = 1.5V of hysteresis at the power supply).

With the three resistors, the UV equation is based on the

simple resistor divider:

1.255 = V

[(R5 + R6)/(R4 + R5 + R6)] or

= 1.255 [(R4 + R5 + R6)/(R5 + R6)]

Similarly, for OV:

1.255 = V

[(R6)/(R4 + R5 + R6)] or

= 1.255 [(R4 + R5 + R6)/(R6)]

Note that there are two equations, but 3 unknowns. Because

of the scale factor, R4 has to be much bigger than the other

two; chose its value first, to set the current (for example, 50V /

500k draws 100A), and then the other two will be in the

10k range. Solve the two equations for two unknowns. Note

that some iteration may be necessary to select values that

meet the requirement, and are also readily available standard

values.

The three resistor divider (R4, R5, R6) is the recommended

approach for most applications, but if acceptable values

FIGURE 33. HARD FAULT SHUTDOWN AND RETRY

ISL6142, ISL6152

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

ISL6142IBZA-T

Mfr. #:

Buy ISL6142IBZA-T

Manufacturer:

Renesas / Intersil

Description:

Hot Swap Voltage Controllers W/ANNEAL 14LD -40+85 WSIDE HOTPLUG CONTRO

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ISL6142IBZA-T

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