20
(but under normal conditions, the FET is on, and the DRAIN
and V
EE
are almost the same voltage).
When any of the 5 conditions occur that turn off the GATE, the
Q3 DMOS turns off, and the resistor and Q2 clamp the
PWRGD pin to one diode drop (~0.7V) above the DRAIN pin.
This should be able to pull low against the module pull-up
current, and disable the module.
Applications: GATE Pin
To help protect the external FET, the output of the GATE pin
is internally clamped; up to an 80V supply and will not be any
higher than 15V. Under normal operation when the supply
voltage is above 20V, the GATE voltage will be regulated to a
nominal 13.6V above V
EE
.
Applications: “Brick” Regulators
One of the typical loads used are DC/DC regulators, some
commonly known as “brick” regulators, (partly due to their
shape, and because it can be considered a “building block”
of a system). For a given input voltage range, there are
usually whole families of different output voltages and
current ranges. There are also various standardized sizes
and pinouts, starting with the original “full” brick, and since
getting smaller (half-bricks and quarter-bricks are now
common).
Other common features may include: all components
(except some filter capacitors) are self-contained in a
molded plastic package; external pins for connections; and
often an ENABLE input pin to turn it on or off. A hot plug IC,
such as the ISL6142 is often used to gate power to a brick,
as well as turn it on.
Many bricks have both logic polarities available (Enable high
or low input); select the ISL6142 (L-version) or ISL6152 (H-
version) to match. There is little difference between them,
although the L-version output is usually simpler to interface.
The Enable input often has a pull-up resistor or current
source, or equivalent built in; care must be taken in the
ISL6152 (H version) output that the given current will create
a high enough input voltage (remember that current through
the RPG 6.2k resistor generates the high voltage level; see
Figure 34).
The input capacitance of the brick is chosen to match its
system requirements, such as filtering noise, and
maintaining regulation under varying loads. Note that this
input capacitance appears as the load capacitance of the
ISL6142/52.
The brick’s output capacitance is also determined by the
system, including load regulation considerations. However, it
can affect the ISL6142/52, depending upon how it is
enabled. For example, if the PWRGD
/PWRGD signal is not
used to enable the brick, the following could occur.
Sometime during the inrush current time, as the main power
supply starts charging the brick input capacitors, the brick
itself will start working, and start charging its output
capacitors and load; that current has to be added to the
inrush current. In some cases, the sum could exceed the
Over-Current threshold, which could shut down the system if
the time-out period is exceeded! Therefore, whenever
practical, it is advantageous to use the PWRGD
/PWRGD
output to keep the brick off at least until the input caps are
charged up, and then start-up the brick to charge its output
caps.
Typical brick regulators include models such as Lucent
JW050A1-E or Vicor VI-J30-CY. These are nominal -48V
input, and 5V outputs, with some isolation between the input
and output.
Applications: Optional Components
In addition to the typical application, and the variations
already mentioned, there are a few other possible
components that might be used in specific cases. See Figure
38 for some possibilities.
If the input power supply exceeds the 100V absolute
maximum rating, even for a short transient, that could cause
permanent damage to the IC, as well as other components
on the board. If this cannot be guaranteed, a voltage
suppressor (such as the SMAT70A, D1) is recommended.
When placed from V
DD
to -V
IN
on the board, it will clamp the
voltage.
If transients on the input power supply occur when the
supply is near either the OV or UV trip points, the GATE
could turn on or off momentarily. One possible solution is to
add a filter cap C4 to the V
DD
pin, through isolation resistor
R11. A large value of R11 is better for the filtering, but be
aware of the voltage drop across it. For example, a 1k
resistor, with 2.4mA of I
DD
would have 2.4V across it and
dissipate 2.4mW. Since the UV and OV comparators are
referenced with respect to V
EE,
they should not be affected,
but the GATE clamp voltage could be offset by the voltage
across the extra resistor.
V
EE
PWRGD
DRAIN
VDD
+
VIN+
VIN-
ON/OFF
VOUT+
VOUT-
CL
Q3
Q2
6.2K
ACTIVE HIGH
ENABLE
MODULE
(SECTION OF) ISL6152
(H VERSION)
+
-
V
PG
+
-
V
EE
GATE
V
GATE
+
-
+
-
LOGIC
LATCH
V
GH
+
-
V
DH
V
EE
+
-
FIGURE 37. ACTIVE HIGH ENABLE MODULE
ISL6142, ISL6152
