22
BOM (Bill Of Materials)
R1 = 0.02 (5%)
R2 =10.0 (5%)
R3 = 18.0K (10%)
R4 = 549K (1%)
R5 = 6.49K (1%)
R6 = 10.0K (1%)
R7 = R8 = 400(1%)
R9 = 4.99K (1%)
R10 = 5.10K (10%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
C3 = 1500pF (25V)
Q1 = IRF530 (100V, 17A, 0.11)
Q2 = N-channel Logic FEFT
G 10
CT 13
VDD 14
4 OV
5 UV
1 PG
ISL6142
GATE
SOURCE
DRAIN
NFET
-48V IN
GND
GND
-48V OUT
2 FLT
3 DIS
6 IS-
7 VEE
S 8
D 11
IS+ 9
IS
O 12
R4
R5
R6
R2
R9
R3
C3
C2
C1
R7
R8
TO
-48V
IN
V
DD
+5V
TO
PIN 9
R1
R10
FIGURE 39. ISL6142 SAMPLE LAYOUT (NOT TO SCALE)
G
D
S
LOGIC IN
-48V
IN
-48V
IN
GND
ISL6142, ISL6152
23
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
ISL6142, ISL6152
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
µ
0.25(0.010) BM M
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or great-
er above the seating plane, shall not exceed a maximum value
of 0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.1890 0.1968 4.80 5.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N8 87
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
ISL6142, ISL6152

ISL6142IBZA-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers W/ANNEAL 14LD -40+85 WSIDE HOTPLUG CONTRO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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