325 MHz, 8 × 8 Buffered Video
Crosspoint Switches
Data Sheet
AD8108/AD8109
Rev. C Document Feedback
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FEATURES
8 × 8 high speed nonblocking switch arrays
AD8108: G = 1
AD8109: G = 2
Serial or parallel programming of switch array
Serial data out allows daisy-chaining of multiple 8 × 8 arrays
to create larger switch arrays
Output disable allows connection of multiple devices
Pin-compatible with AD8110/AD8111 16 × 8 switch arrays
For 16 × 16 arrays see AD8116
Complete solution
Buffered inputs
Eight output amplifiers
AD8108 (G = 1)
AD8109 (G = 2)
Drives 150 Ω loads
Excellent video performance
60 MHz 0.1 dB gain flatness
0.02%/0.02° differential gain/differential phase error
(R
L
= 150 Ω)
Excellent ac performance
3 dB bandwidth: 325 MHz (AD8108), 250 MHz (AD8109)
Slew rate: 400 V/µs (AD8108), 480 V/µs (AD8109)
Low power of 45 mA
Low all hostile crosstalk of 83 dB at 5 MHz
Reset pin allows disabling of all outputs (connected through
a capacitor to ground provides power-on reset capability)
Excellent ESD rating: exceeds 4000 V human body model
80-lead LQFP (12 mm × 12 mm)
APPLICATIONS
Routing of high speed signals including
Composite video (NTSC, PAL, S, SECAM)
Component video (YUV, RGB)
Compressed video (MPEG, Wavelet)
3-level digital video (HDB3)
GENERAL DESCRIPTION
The AD8108/AD8109 are high speed 8 × 8 video crosspoint
switch matrices. They offer a 3 dB signal bandwidth greater than
250 MHz and channel switch times of less than 25 ns with 1%
settling. With 83 dB of crosstalk and 98 dB isolation (at 5 MHz),
the AD8108/AD8109 are useful in many high speed applications.
The differential gain and differential phase of better than 0.02%
FUNCTIONAL BLOCK DIAGRAM
AD8108/AD8109
SWITCH
MATRIX
OUTPUT
BUFFER
G = +1
G = +2
32
32
64
32-BIT SHIFT REGISTER
WITH 4-BIT
PARALLEL LOADING
PARALLEL LATCH
DECODE
8
× 4:8 DECODERS
8
CLK
DATA IN
UPDATE
CE
RESET
8 INPUTS
A0
DATA
OUT
8 OUTPUTS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO "OFF"
A1
A2
SER/PAR
D0 D1
D2
D3
ENABLE/DISABLE
01068-001
Figure 1. Functional Block Diagram
and 0.02°, respectively, along with 0.1 dB flatness out to 60 MHz,
make the AD8108/AD8109 ideal for video signal switching.
The AD8108 and AD8109 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8108 has a gain of 1, while the AD8109
offers a gain of 2. They operate on voltage supplies of ±5 V
while consuming only 45 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control allowing updating of an individual output without
reprogramming the entire array.
The AD8108/AD8109 is packaged in an 80-lead LQFP and is
available over the extended industrial temperature range of
40°C to +85°C.
AD8108/AD8109 Data Sheet
Rev. C | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
AD8108/AD8109—Specifications .................................................. 3
Timing Characteristics (Serial) .................................................. 5
Timing Characteristics (Parallel) ............................................... 6
Absolute Maximum Ratings ............................................................ 8
Maximum Power Dissipation ..................................................... 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Input/Output Schematics .............................................................. 17
Theory of Operation ...................................................................... 18
Applications ................................................................................ 18
Power-On
RESET
....................................................................... 19
Gain Selection ............................................................................. 19
Creating Larger Crosspoint Arrays .......................................... 20
Multichannel Video ................................................................... 21
Crosstalk ...................................................................................... 22
PCB Layout ...................................................................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
5/2016Rev. B to Rev. C
Changes to Crosstalk, All Hostile Parameter and Off Isolation,
Input-Output Parameter, Table 3 .................................................... 3
Changes to Areas of Crosstalk Section ........................................ 22
Changes to PCB Layout Section ................................................... 24
Deleted Figure 52; Renumbered Sequentially ............................ 24
Deleted Figure 53 and Figure 54 ................................................... 25
Moved Outline Dimensions and Ordering Guide ..................... 25
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
Deleted Figure 55 and Figure 56 ................................................... 26
Deleted Figure 57 ............................................................................ 27
Deleted Evaluation Board Section, Control the Evaluation
Board from a PC Section, Figure 58, Overshoot of PC Printer
Ports’ Data Lines Section, and Figure 59 ..................................... 28
Deleted Figure 60 ............................................................................ 29
9/2005Rev. A to Rev. B
Updated Format .................................................................. Universal
Change to Absolute Maximum Ratings ......................................... 8
Changes to Maximum Power Dissipation Section ........................ 8
Change to Figure 4 ............................................................................ 8
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
1/2002Rev. 0 to Rev. A
Changed MQFP to LQFP .................................................. Universal
Updated Outline Dimensions ....................................................... 27
10/1997Revision 0: Initial Version
Data Sheet AD8108/AD8109
Rev. C | Page 3 of 27
SPECIFICATIONS
V
S
= ±5 V, T
A
= +25°C, R
L
= 1 kΩ, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit Reference
DYNAMIC PERFORMANCE
−3 dB Bandwidth 200 mV p-p, R
L
= 150
240/150 325/250 MHz Figure 1, Figure 13
2 V p-p, R
L
= 150
140/160 MHz Figure 1, Figure 13
Propagation Delay 2 V p-p, R
L
= 150
5 ns
Slew Rate 2 V Step, R
L
= 150
400/480 V/µs
Settling Time 0.1%, 2 V Step, R
L
= 150 40 ns Figure 15, Figure 18
Gain Flatness
0.05 dB, 200 mV p-p, R
L
= 150
60/50
MHz
Figure 1, Figure 13
0.05 dB, 2 V p-p, R
L
= 150
60/50 MHz Figure 1, Figure 13
0.1 dB, 200 mV p-p, R
L
= 150
70/65 MHz Figure 1, Figure 13
0.1 dB, 2 V p-p, R
L
= 150
80/50 MHz Figure 1, Figure 13
NOISE/DISTORTION PERFORMANCE
Differential Gain Error NTSC or PAL, R
L
= 1 k
0.01 %
NTSC or PAL, R
L
= 150
0.02 %
Differential Phase Error NTSC or PAL, R
L
= 1 k
0.01 Degrees
NTSC or PAL, R
L
= 150 0.02 Degrees
Crosstalk, All Hostile f = 5 MHz −83/−85 dB Figure 8, Figure 14
f = 10 MHz −76/−83 dB Figure 8, Figure 14
Off Isolation, Input-Output
f = 5 MHz, R
L
=150 Ω, one
channel
−98/−102 dB Figure 23, Figure 29
Input Voltage Noise 0.01 MHz to 50 MHz 15
nV/
Hz
Figure 20, Figure 26
DC PERFORMANCE
Gain Error R
L
= 1 k
0.04/0.1 0.07/0.5 %
R
L
= 150 0.15/0.25 %
Gain Matching
No load, channel-channel
0.02/1.0
%
R
L
= 1 kΩ, channel-channel
0.09/1.0 %
Gain Temperature Coefficient 0.5/8 ppm/°C
OUTPUT CHARACTERISTICS
Output Impedance DC, enabled 0.2 Figure 24, Figure 30
Disabled 10/0.001 MΩ
Figure 21, Figure 27
Output Disable Capacitance Disabled 2 pF
Output Leakage Current Disabled, AD8108 only 1/NA µA
Output Voltage Range
No load
±3
V
Output Current 20 40 mA
Short-Circuit Current 65 mA
INPUT CHARACTERISTICS
Input Offset Voltage Worst case (all configurations) 5 20 mV Figure 35, Figure 41
Temperature coefficient 12 µV/°C Figure 36, Figure 42
Input Voltage Range ±2.5/±1.25 ±3/±1.5 V
Input Capacitance Any switch configuration 2.5 pF
Input Resistance 1 10 MΩ
Input Bias Current
Per output selected
2
5
µA
SWITCHING CHARACTERISTICS
Enable On Time 60 ns
Switching Time, 2 V Step
50%
UPDATE to 1% settling
25 ns
Switching Transient (Glitch) Measured at output 20/30 mV p-p Figure 22, Figure 28

AD8109ASTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog & Digital Crosspoint ICs 325 MHz 8 x 8 Buffered
Lifecycle:
New from this manufacturer.
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