OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD8109ASTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
AD8108/AD8109 Data Sheet
Rev. C | Page 4 of 27
Parameter Test Conditions/Comments Min Typ Max Unit Reference
POWER SUPPLIES
Supply Current AVCC, outputs enabled, no load 33 mA
AVCC, outputs disabled 10 mA
AVEE, outputs enabled, no load 33 mA
AVEE, outputs disabled
10
mA
DVCC 10 mA
Supply Voltage Range ±4.5 to ±5.5 V
PSRR f = 100 kHz 73/78 dB Figure 19, Figure 25
f = 1 MHz 55/58 dB
OPERATING TEMPERATURE RANGE
Temperature Range Operating (still air) −40 to +85
°C
θ
JA
Operating (still air) 48
°C/W
Data Sheet AD8108/AD8109
Rev. C | Page 5 of 27
TIMING CHARACTERISTICS (SERIAL)
Table 2. Timing Characteristics
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time
t
1
20
ns
CLK Pulse Width t
2
100 ns
Serial Data Hold Time t
3
20 ns
CLK Pulse Separation, Serial Mode t
4
100 ns
CLK to UPDATE Delay
t
5
0 ns
UPDATE Pulse Width
t
6
50 ns
CLK to DATA OUT Valid, Serial Mode
t
7
180
ns
Propagation Delay, UPDATE to Switch On or Off
– 8 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 6.4 µs
CLK, UPDATE Rise and Fall Times
– 100 ns
RESET Time
– 200 ns
Table 3. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
RESET, SER/PAR
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 µA max
−400 µA min
−400 µA max
3.0 mA min
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
1
0
1
0
DATA IN
CLK
1 = LATCHED
0 = TRANSPARENT
DATA OUT
OUT7 (D3)
OUT7 (D2)
OUT00 (D0)
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
7
t
1
t
3
t
6
t
2
t
4
t
5
UPDATE
01068-002
Figure 2. Timing Diagram, Serial Mode
AD8108/AD8109 Data Sheet
Rev. C | Page 6 of 27
TIMING CHARACTERISTICS (PARALLEL)
Table 4. Timing Characteristics
Parameter Symbol Min Typ Max Unit
Data Setup Time
t
1
20
ns
CLK Pulse Width t
2
100
ns
Data Hold Time t
3
20
ns
CLK Pulse Separation
t
4
100
ns
CLK to UPDATE Delay
t
5
0
ns
UPDATE Pulse Width
t
6
50
ns
Propagation Delay, UPDATE to Switch On or Off
–
8 ns
CLK, UPDATE Rise and Fall Times
–
100 ns
RESET Time
– 200
ns
Table 5. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DATA OUT DATA OUT
RESET, SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
RESET SER/PAR
CLK, D0, D1, D2,
D3, A0, A1, A2
CE, UPDATE
DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max −400 µA min −400 µA max 3.0 mA min
1
0
1
0
D0–D3
A0–A2
CLK
1 = LATCHED
UPDATE
0 = TRANSPARENT
t
2
t
1
t
5
t
6
t
3
t
4
01068-003
Figure 3. Timing Diagram, Parallel Mode
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

AD8109ASTZ

Mfr. #:
Buy AD8109ASTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog & Digital Crosspoint ICs 325 MHz 8 x 8 Buffered
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet