AD8108/AD8109 Data Sheet
Rev. C | Page 18 of 27
THEORY OF OPERATION
The AD8108 (G = 1) and AD8109 (G = 2) share a common core
architecture consisting of an array of 64 transconductance (gm)
input stages organized as eight 8:1 multiplexers with a common
8-line analog input bus. Each multiplexer is basically a folded-
cascode, high impedance voltage feedback amplifier with eight
input stages. The input stages are NPN differential pairs whose
differential current outputs are combined at the output stage,
which contains the high impedance node, compensation and a
complementary emitter follower output buffer. In the AD8108,
the output of each multiplexer is fed back directly to the
inverting inputs of its eight gm stages. In the AD8109, the
feedback network is a voltage divider consisting of two equal
resistors.
This switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back terminated video load
(150 Ω) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02°, respectively). This
design also achieves high input resistance and low input
capacitance without the signal degradation and power
dissipation of additional input buffers. However, the small input
bias current at any input increases almost linearly with the
number of outputs programmed to that input.
The output disable feature of these crosspoints allows larger
switch matrices to be built by simply busing together the
outputs of multiple 8 × 8 ICs. However, while the disabled
output impedance of the AD8108 is very high (10 MΩ), that of
the AD8109 is limited by the resistive feedback network (which
has a nominal total resistance of 1 kΩ) that appears in parallel
with the disabled output. If the outputs of multiple AD8109
devices are connected through separate back termination
resistors, the loading due to these finite output impedances
lowers the effective back termination impedance of the overall
matrix. This problem is eliminated if the outputs of multiple
AD8109 devices are connected directly and share a single back
termination resistor for each output of the overall matrix. This
configuration increases the capacitive loading of the disabled
AD8109 devices on the output of the enabled AD8109.
APPLICATIONS
The AD8108/AD8109 have two options for changing the
programming of the crosspoint matrix. In the first, a serial word
of 32 bits can be provided that updates the entire matrix each
time. The second option allows for changing the programming
of a single output via a parallel interface. The serial option
requires fewer signals, but requires more time (clock cycles) for
changing the programming, while the parallel programming
technique requires more signals, but can change a single output
at a time and requires fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the device pins
CE
, CLK,
DATA IN,
UPDATE
, and
SER
/PAR. The first step is to assert a
low on
SER
/PAR to enable the serial programming mode.
CE
for the chip must be low to allow data to be clocked into the
device. The
CE
signal can be used to address an individual
device when devices are connected in parallel.
The
UPDATE
signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when
UPDATE
is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 32 data bits must be shifted in to complete the
programming. For each of the eight outputs, there are three bits
(D0 to D2) that determine the source of its input followed by
one bit (D3) that determines the enabled state of the output. If
D3 is low (output disabled), the three associated bits (D0 to D2)
do not matter because no input is switched to that output.
The most significant output address data is shifted in first and is
followed in sequence until the least significant output address
data is shifted in. At this point,
UPDATE
can be taken low,
which causes the programming of the device according to the
data that was just shifted in. The
UPDATE
registers are
asynchronous, and when
UPDATE
is low, they are transparent.
If more than one AD8108/AD8109 device is to be serially
programmed in a system, the DATA OUT signal from one device
can be connected to the DATA IN of the next device to form a
serial chain. All of the CLK,
CE
,
UPDATE
, and
SER
/PAR pins
should be connected in parallel and operated as described above.
The serial data is input to the DATA IN pin of the first device of
the chain, and it ripples on through to the last. Therefore, the
data for the last device in the chain should come at the beginning
of the programming sequence. The length of the programming
sequence is 32 times the number of devices in the chain.
Parallel Programming
While using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification of
a single output at a time. Since this takes only one CLK/
UPDATE
cycle, significant time savings can be realized by using parallel
programming.
One important consideration in using parallel programming is
that the
RESET
signal does not reset all registers in the AD8108/
AD8109. When taken low, the
RESET
signal only sets each
