Data Sheet AD7228
Rev. C | Page 9 of 15
Interface Logic Information
The A0, A1, and A2 address lines select which DAC accepts
data from the input port. Table 6 shows the selection table for
the eight DACs and Figure 8 shows the input control logic.
When the
WR
signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of
WR
. While
WR
is high, the analog outputs
remain at the value corresponding to the data held in their
respective latches.
Table 6. AD7228 Truth Table
Control Inputs
Operation
WR
A2 A1 A0
High X
1
X X
No operation, device
not selected
Low Low Low Low DAC 1 transparent
Low to High Low Low Low DAC 1 latched
Low Low Low High DAC 2 transparent
Low Low High Low DAC 3 transparent
Low Low High High DAC 4 transparent
Low High Low Low DAC 5 transparent
Low High Low High DAC 6 transparent
Low High High Low DAC 7 transparent
Low High High High DAC 8 transparent
1
X means don’t care.
A0
TO DAC 1 LATCH
A1
A2
W
R
TO DAC 2 LATCH
TO DAC 3 LATCH
TO DAC 4 LATCH
TO DAC 5 LATCH
TO DAC 6 LATCH
TO DAC 7 LATCH
TO DAC 8 LATCH
1-OF-8
DECODER
13034-002
Figure 8. Input Control Logic
Supply Current
The AD7228 has a maximum I
DD
specification of 20 mA and a
maximum I
SS
of 18 mA over the −40°C to +85°C temperature
range. Figure 9 shows a typical plot of power supply current vs.
temperature.
V
DD
= +15V
V
SS
= –5V
I
DD
I
SS
POWER SUPPLY CURRENT (mA)
16
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–60 –40 –20 0 20 40
TEMPERATURE (°C)
60 80 100 120 140
–14
13034-009
Figure 9. Power Supply Current vs. Temperature
Applying the AD7228 Unipolar Output Operation
Unipolar output operation is the basic mode of operation for
each channel of the AD7228 and the output voltage has the same
positive polarity as V
REF
. Connections for unipolar output operat-
ion are shown in Figure 10. The AD7228 can be operated from
single or dual supplies. The voltage at the reference input must
never be negative with respect to GND. Failure to observe this
precaution may cause parasitic transistor action and possible
device destruction. The code table for unipolar output operation
is shown in Table 7.
V
SS
GND
LATCH 5 DAC 5
LATCH 6 DAC 6
LATCH 7 DAC 7
LATCH 8
CONTROL
LOGIC
DAC 8
V
OUT8
8
WR
A1
A0
A2
AD7228
10 12
2
3
4
5
6
7
8
9
21
22
23
24
11 1
V
OUT7
7
V
OUT6
6
V
OUT5
5
V
OUT4
4
V
OUT3
3
V
OUT2
2
V
OUT1
1
LATCH 1 DAC 1
LATCH 2 DAC 2
LATCH 3 DAC 3
LATCH 4 DAC 4
DATA BUS
V
REF
V
DD
+12V TO +15V
DATA
BUS
MSB
LSB
0V OR –5V
13
20
13034-010
Figure 10. Unipolar Output Circuit
AD7228 Data Sheet
Rev. C | Page 10 of 15
Table 7. Unipolar Code Table
DAC Latch Contents
MSB LSB
1
Analog Output
1 1 1 1 1 1 1 1 +V
REF
(255/256)
1 0 0 0 0 0 0 1 +V
REF
(129/256)
1 0 0 0 0 0 0 0
+V
REF
2256
128
REF
V
0 1 1 1 1 1 1 1 +V
REF
(127/256)
0 0 0 0 0 0 0 1 +V
REF
(1/256)
0 0 0 0 0 0 0 0 0 V
1
1 LSB = (V
REF
)(2
−8
) = V
REF
(1/256).
Bipolar Output Operation
Each of the DACs on the AD7228 can be individually configured
for bipolar output operation. This is possible using one external
amplifier and two resistors per channel. Figure 11 shows a circuit
used to implement offset binary coding (bipolar operation) with
DAC 1 of the AD7228. In this case,
)()(1
1
REFREF
OUT
V
R1
R2
VD
R1
R2
V
With R1 = R2,
V
OUT
= (2D
1
− 1) × (V
REF
)
where D
1
is a fractional representation of the digital word in
Latch 1 of the AD7228 (0 ≤ D
1
≤ 255/256).
Table 8. Bipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1 1 1 1 1 1 1 1 +V
REF
(127/128)
1 0 0 0 0 0 0 1 +V
REF
(1/128)
1 0 0 0 0 0 0 0 0 V
0 1 1 1 1 1 1 1 −V
REF
(1/128)
0 0 0 0 0 0 0 1 −V
REF
(127/128)
0 0 0 0 0 0 0 0 −V
REF
(128/128) = −V
REF
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over temperature.
The AD7228 can be operated from a single supply or from dual
supplies. Table 8 shows the digital code vs. output voltage
relationship for the circuit of Figure 11 with R1 = R2.
AC Reference Signal
In some applications, it may be desirable to have an ac signal
applied as the reference input to the AD7228. The AD7228 has
multiplying capability within the upper (10 V) and lower (2 V)
limits of reference voltage when operated with dual supplies.
Therefore, ac signals must be ac-coupled and biased up before
being applied to the reference input. Figure 12 shows an ac
signal applied to the reference input of the AD7228. For input
frequencies up to 50 kHz, the output distortion typically remains
less than 0.1%. The typical 3 dB bandwidth for small signal
inputs is 800 kHz.
12
9
11 1
GND
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
SS
V
DD
V
OUT
V
OUT
1
R1
10k
±0.1%
R2
10k
±0.1%
+15V
–15V
V
REF
AD7228*
V
REF
10
DAC 1
13034-011
Figure 11. Bipolar Output Circuit
+10V
REFERENCE
INPUT
15k
+15V
–5V
10k
+2V
12
9
11 1
GND
*
ADDITION
A
L PINS OMITTED FOR CLARITY.
V
SS
V
DD
V
OUT
1
V
REF
+15V
AD7228*
10
DAC 1
+4V
–4V
13034-012
Figure 12. Applying an AC Signal to the AD7228
Data Sheet AD7228
Rev. C | Page 11 of 15
Timing Deskew
Signal edges slowing or rounding off by the time they reach the
pin driver circuitry is a common problem in automated test
equipment (ATE) applications. Square up the edge at the pin
driver to overcome this problem. However, because each edge is
not rounded off by the same extent, this squaring up may lead
to incorrect timing relationship between signals. This effect is
shown in Figure 13.
BUFFER TRIGGER POINT
HIGH-SPEED
BUFFER
13034-013
Figure 13. Time Skewing Due to Slowing of Edges
The circuit of Figure 14 shows how two DACs of the AD7228
can help overcome the problem of time skewing. The same two
signals are applied to this circuit as are applied in Figure 14. The
output of each DAC is applied to one input of a high speed
comparator, and the signals are applied to the other inputs.
Varying the output voltage of the DAC effectively varies the
trigger point at which the comparator flips. Therefore, the timing
relationship between the two signals can be programmably
corrected (or deskewed) by varying the code to the DAC of
the AD7228. In a typical application, the code is loaded to the
DACs for correct timing relationships during the calibration
cycle of the instrument.
POSITION OF THIS EDGE
PROGRAMMED BY CODE
TO DAC2
*ADDITION
A
L PINS OMITTED FOR CLARITY.
POSITION OF THIS EDGE
PROGRAMMED BY CODE
TO DAC1
HIGH-SPEED
COMPARATORS
V
REF
AD7228*
V
SS
V
DD
V
OUT
2
V
OUT
1
GND
11 1
10 12
9
8
13034-014
Figure 14. AD7228 Timing Deskew Circuit
Coarse/Fine Adjust
Pair the DACs on the AD7228 together to form a coarse/fine
adjust function as shown in Figure 15. The function is achieved
using one external op amp and a few resistors per pair of DACs.
DAC 1 is the most significant or coarse DAC. Data is first loaded to
this DAC to coarsely set the output voltage. DAC 2 is then used
to fine tune this output voltage. Varying the ratio of R1 to R2
varies the relative effect of the coarse and fine DACs on the
output voltage. For the resistor values shown, DAC 2 has a
resolution of 150 μV in a 10 V output range. Because each DAC
on the AD7228 is guaranteed monotonic, the coarse adjustment
and fine adjustment are each monotonic. One application for
this is as a setpoint controller (see the AN-317 Application
Note, “Circuit Applications of the AD7226 Quad CMOS DAC,
available from Analog Devices, Inc.).
12
8
11 1
GND
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
SS
–5V
DD
V
OUT
2
REF
AD7228*
10
DAC 2
9
V
OUT
1
200
51.2k 200
V
OUT
51.2k
DAC 1
A1
13034-015
Figure 15. Coarse/Fine Adjust Circuit
Self Programmable Reference
The circuit of Figure 16 shows how one DAC of the AD7228, in
this case DAC 1, can be used in a feedback configuration to
provide a programmable reference for itself and the other seven
converters. The relationship of V
REF
to V
IN
is expressed by
INREF
V
DG
G
V
)1(
)1(
1
where G = R2/R1.
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD7228*
9
V
OUT
1
A1
R2R1
V
IN
12
GND
V
SS
–5V
+15V
10
11 1
V
DD
V
REF
13034-016
Figure 16. Self Programmable Reference

AD7228KRZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 8-BIT OCTAL CMOS IC
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