Data Sheet AD7228
Rev. C | Page 3 of 15
SPECIFICATIONS
DUAL SUPPLY
V
DD
= 10.8 V to 16.5 V, V
SS
= −5 V ± 10%, GND = 0 V, V
REF
= 2 V to 10 V, R
L
= 2 kΩ, C
L
= 100 pF, unless otherwise noted. All
specifications T
MIN
to T
MAX
, −40°C to +85°C unless otherwise noted. V
OUT
must be less than V
DD
by 3.5 V to ensure correct operation.
Table 1.
Parameter
K and B
Versions
L and C
Versions Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 8 8 Bits
Total Unadjusted Error (TUE)
1
±2 ±1 LSB max V
DD
= 15 V ± 10%, V
REF
= 10 V
Relative Accuracy ±1 ±1/2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic
Full-Scale Error
2
±1 ±1/2 LSB max
Typical temperature coefficient is 5 ppm/°C with
V
REF
= 10 V
Zero Code Error
at 25°C ±25 ±15 mV max Typical temperature coefficient is 30 μV/°C
T
MIN
to T
MAX
±30 ±20 mV max
Minimum Load Resistance 2 2 kΩ min V
OUT
= 10 V
REFERENCE INPUT
Voltage Range 2/10 2/10 V min/V max
Input Resistance 2 2 kΩ min
Input Capacitance
3
500 500 pF max Occurs when each DAC is loaded with all 1s
AC Feedthrough −70 −70 dB typ V
REF
= 8 V p-p sine wave at 10 kHz
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Leakage Current ±1 ±1 μA max V
IN
= 0 V or V
DD
Input Capacitance
3
8 8 pF max
Input Coding Binary Binary
DYNAMIC PERFORMANCE
3
Voltage Output Slew Rate 2 2 V/μs min
Voltage Output Settling Time
Positive Full-Scale Change 5 5 μs max V
REF
= 10 V; settling time to ±1/2 LSB
Negative Full-Scale Change 5 5 μs max V
REF
= 10 V; settling time to ±1/2 LSB
Digital Feedthrough 50 50 nV-sec typ
Code transition all 0s to all 1s, V
REF
= 0 V; WR = V
DD
Digital Crosstalk
4
50 50 nV-sec typ
Code transition all 0s to all 1s, V
REF
= 10 V; WR = 0 V
POWER SUPPLIES
V
DD
Range 10.8/16.5 10.8/16.5 V min/V max For specified performance
V
SS
Range −4.5/−5.5 −4.5/−5.5 V min/V max For specified performance
I
DD
Outputs unloaded; V
IN
= V
INL
or V
INH
at 25°C 16 16 mA max
T
MIN
to T
MAX
20 20 mA max
I
SS
Outputs unloaded; V
IN
= V
INL
or V
INH
at 25°C 14 14 mA max
T
MIN
to T
MAX
18 18 mA max
1
Total unadjusted error includes zero code error, relative accuracy, and full-scale error.
2
Calculated after zero code error is adjusted out.
3
Sample tested at T
A
= 25°C to ensure compliance.
4
The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.
AD7228 Data Sheet
Rev. C | Page 4 of 15
SINGLE SUPPLY
V
DD
= 15 V ± 10%, V
SS
= GND, GND = 0 V, V
REF
= 10 V, R
L
= 2 kΩ, C
L
= 100 pF, unless otherwise noted. All specifications T
MIN
to T
MAX
,
−40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
K and B
Versions
L and C
Versions Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 8 8 Bits
Total Unadjusted Error
1
±2 ±1 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic
Minimum Load Resistance 2 2 kΩ min V
OUT
= 10 V
REFERENCE INPUT
Input Resistance 2 2 kΩ min
Input Capacitance
2
500 500 pF max Occurs when each DAC is loaded with all 1s
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Leakage Current ±1 ±1 μA max V
IN
= 0 V or V
DD
Input Capacitance
2
8 8 pF max
Input Coding Binary Binary
DYNAMIC PERFORMANCE
2
Voltage Output Slew Rate 2 2 V/μs min
Voltage Output Settling Time
Positive Full-Scale Change 5 5 μs max Settling time to ±1/2 LSB
Negative Full-Scale Change 7 7 μs max Settling time to ±1/2 LSB
Digital Feedthrough 50 50 nV-sec typ
Code transition all 0s to all 1s, V
REF
= 0 V, WR = V
DD
Digital Crosstalk
3
50 50 nV-sec typ
Code transition all 0s to all 1s, V
REF
= 10 V, WR = 0 V
POWER SUPPLIES
V
DD
Range 13.5/16.5 13.5/16.5 V min/V max For specified performance
I
DD
Outputs unloaded; V
IN
= V
INL
or V
INH
at 25°C 16 16 mA max
T
MIN
to T
MAX
20 20 mA max
1
Total unadjusted error includes zero code error, relative accuracy and full-scale error.
2
Sample tested at T
A
= 25°C to ensure compliance.
3
The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.
Data Sheet AD7228
Rev. C | Page 5 of 15
SWITCHING CHARACTERISTICS
See Figure 8 and Figure 2; V
DD
= 5 V ± 5% or 10.8 V to 16.5 V; V
SS
= 0 V or –5 V ± 10%. Sample tested at 25°C to ensure compliance. All
input rise and fall times measured from 10% to 90% of 5 V, t
R
= t
F
= 5 ns. Timing measurement reference level is (V
INH
+ V
INL
)/2.
Table 3.
Parameter
Limit at 25°C,
All Grades
Limit at T
MIN
, T
MAX
,
K, L, B, and C Versions Unit Description
t
1
0 0 ns min
Address to WR
setup time
t
2
0 0 ns min
Address to WR
hold time
t
3
70 90 ns min
Data valid to WR
setup time
t
4
10 10 ns min
Data valid to WR
hold time
t
5
95 120 ns min Write pulse width
t
2
5V
0V
5V
V
INH
V
INL
0V
5V
0V
WR
A
DDRESS
NOTES
1. THE SELECTED INPUT LATCH IS TRANSPARENT WHILE WR
IS LOW, THUS INVALID DATA DURING THIS TIME CAN
CAUSE SPURIOUS OUTPUTS.
DATA
t
4
t
1
t
5
t
3
13034-003
Figure 2. Write Cycle Timing Diagram

AD7228KRZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 8-BIT OCTAL CMOS IC
Lifecycle:
New from this manufacturer.
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