AD7228 Data Sheet
Rev. C | Page 8 of 15
THEORY OF OPERATION
CIRCUIT INFORMATION
DACs
The AD7228 contains eight identical, 8-bit, voltage mode DACs.
The output voltages from the converters have the same polarity
as the reference voltage, allowing single-supply operation. A
novel DAC switch pair arrangement on the AD7228 allows a
reference voltage range from 2 V to 10 V. Each DAC consists of
a highly stable, thin film, R-2R ladder and eight high speed
NMOS switches. The simplified circuit diagram for one channel
is shown in Figure 5. Note that V
REF
and GND are common to
all eight DACs.
RRR
2R
DB7
2R
DB6
2R
DB5
V
REF
V
OUT
NOTES
1. SHOWN FOR ALL 1s ON DAC.
GND
2R
DB0
2R
13034-006
Figure 5. DAC Simplified Circuit Diagram
The input impedance at the V
REF
pin of the AD7228 is the parallel
combination of the eight individual DAC reference input imp-
edances. It is code dependent and can vary from 2 kΩ to infinity.
The lowest input impedance occurs when all eight DACs are
loaded with digital code 01010101. Therefore, it is important
that the external reference source presents a low output imp-
edance to the V
REF
terminal of the AD7228 under changing load
conditions. Due to transient currents at the reference input during
digital code changes, a 0.1 μF (or greater) decoupling capacitor is
recommended on the V
REF
input for dc applications. The nodal
capacitance at the reference terminal is also code dependent
and typically varies from 120 pF to 350 pF.
Consider each V
OUTX
pin as a digitally programmable voltage
source with an output voltage.
V
OUTx
= D
N
× V
REF
where D
N
is a fractional representation of the digital input code
and can vary from 0 to 255/256.
The output impedance is that of the output buffer amplifier as
described in the Op Amp section.
Op Amp
Each voltage mode DAC output is buffered by a unity-gain,
noninverting, CMOS amplifier. This buffer amplifier is tested
with a 2 kΩ and 100 pF load, but typically drives a 2 kΩ and
500 pF load.
The AD7228 can be operated from single or dual supplies.
Operating the device from single or dual supplies has no effect
on the positive going settling time. However, the negative going
settling time to voltages near 0 V in single-supply operation is
slightly longer than the settling time for dual supply operation.
Additionally, to ensure that the output voltage can go to 0 V in
single-supply operation, a transistor on the output acts as a
passive pull-down as the output voltage nears 0 V. As a result,
the sink capability of the amplifier is reduced as the output
voltage nears 0 V in single-supply operation. In dual supply
operation, the full sink capability of 400 μA at 25°C is maintained
over the entire output voltage range. The single-supply output
sink capability is shown in Figure 6. The negative V
SS
also gives
improved output amplifier performance, allowing an extended
input reference voltage range and giving an improved slew rate
at the output.
600
500
400
300
200
100
0
123456
OUTPUT VOLTAGE (V)
I
SINK
(µA)
78910
V
DD
= +15V
V
SS
= 0V
T
A
= –55°C
T
A
= +25°C
T
A
= +125°C
13034-007
Figure 6. Single Supply Sink Current
The output broadband noise from the amplifier is 300 μV p-p.
Figure 7 shows a plot of noise spectral density vs. frequency.
700
600
500
400
300
200
100
0
FREQUENCY (Hz)
100 1k 10k 100k
NOISE SPECTRAL DENSITY (nV/√Hz)
13034-008
V
DD
= +15V
V
SS
= –5V
T
A
= 25°C
Figure 7. Noise Spectral Density vs. Frequency
Digital Inputs
The AD7228 digital inputs are compatible with either TTL or
5 V CMOS levels. All logic inputs are static protected MOS
gates with typical input currents of less than 1 nA. Internal
input protection is achieved by on-chip distributed diodes.
