19
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
5.6 Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is
detected, the Supply Controller performs a sequence which automatically reenables the core
power supply and the SRAM power supply, if they are not already enabled.
Figure 5-4. Wake-up Source
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
Falling/Rising
Edge
Detector
WKUPT0
Falling/Rising
Edge
Detector
WKUPT1
Falling/Rising
Edge
Detector
WKUP0
WKUP1
RTTEN
rtt_alarm
20
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
5.7 Fast Startup
The SAM3S8/SD8 allows the processor to restart in a few microseconds while the processor is
in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of
the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-
up signal to the Power Management Controller. As soon as the fast start-up signal is asserted,
the PMC automatically restarts the embedded 4 MHz Fast RC oscillator, switches the master
clock on this 4MHz clock and reenables the processor clock.
Figure 5-5. Fast Start-Up Sources
RTCEN
rtc_alarm
RTTEN
rtt_alarm
USBEN
usb_wakeup
fast_restart
WKUP15
FSTT15
WKUP1
WKUP0
FSTT0
FSTT1
Falling/Rising
Edge
Detector
Falling/Rising
Edge
Detector
Falling/Rising
Edge
Detector
21
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
6. Input/Output Lines
The SAM3S8/SD8 has several kinds of input/output (I/O) lines such as general purpose I/Os
(GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities
of the PIO controllers. The same PIO line can be used whether in I/O mode or by the multiplexed
peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.
6.1 General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such
as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing
or input change interrupt. Programming of these modes is performed independently for each I/O
line through the PIO controller user interface. For more details, refer to the product “PIO Control-
ler” section.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM3S8/SD8 embeds high speed pads able to handle up to 32 MHz for HSMCI (MCK/2),
45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section of the
datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). It consists of
an internal series resistor termination scheme for impedance matching between the driver out-
put (SAM3S8/SD8) and the PCB trace impedance preventing signal reflection. The series
resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also
decreases overshoot and undershoot (ringing) due to inductance of interconnect between
devices or between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
6.2 System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few.
Described below in Table 6-1are the SAM3S8/SD8 system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup the
default function of these pins is always used.
PCB Trace
Z0 ~ 50 Ohms
Receiver
SAM3 Driver with
Rodt
Zout ~ 10 Ohms
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.

ATSAM3SD8BA-MU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
ARM Microcontrollers - MCU QFN,Grn, IT, MRL A
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