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11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
7.5 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in the following table.
7.6 Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-3. SAM3S8_SD8 Master to Slave Access
Slaves
Masters 0 1 2 3
Cortex-M3 I/D
Bus
Cortex-M3 S
Bus
PDC CRCCU
0 Internal SRAM - X X X
1 Internal ROM X - X X
2 Internal Flash X - - X
3 External Bus Interface - X X X
4 Peripheral Bridge - X X -
Table 7-4. Peripheral DMA Controller
Instance name Channel T/R
USART2 Transmit
USART2 Receive
PWM Transmit
TWI1 Transmit
TWI0 Transmit
UART1 Transmit
UART0 Transmit
USART1 Transmit
USART0 Transmit
DACC Transmit
SPI Transmit
