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11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
9. Memories
9.1 Embedded Memories
9.1.1 Internal SRAM
The SAM3S8 device (512-Kbytes, single bank flash) embeds a total of 64-Kbytes high-speed
SRAM.
The SAM3SD8 device (512-Kbytes, dual bank flash) embeds a total of 64-Kbytes high-speed
SRAM.
The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and
0x23FF FFFF.
9.1.2 Internal ROM
The SAM3S8/SD8 embeds an Internal ROM, which contains the SAM Boot Assistant
(SAM-BA
®
), In Application Programming routines (IAP) and Fast Flash Programming Interface
(FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
9.1.3 Embedded Flash
9.1.3.1 Flash Overview
The Flash of the SAM3S8 (512-Kbytes single bank flash) is organized in one bank of 2048
pages of 256 bytes.
The Flash of the SAM3SD8 (512-Kbytes, dual bank flash) is organized in two banks of 1024
pages of 256 bytes each.
The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
9.1.3.2 Flash Power Supply
The Flash is supplied by VDDCORE.
9.1.3.3 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the mas-
ters of the system. It enables reading the Flash and writing the write buffer. It also contains a
User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-
bit internal bus. Its 128-bit wide memory interface increases performance.
The user can choose between high performance or lower current consumption by selecting
either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking
sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
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SAM3S8/SD8 Summary
9.1.3.4 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to the “AC Characteristics” sub-section of the product “Electrical
Characteristics”.
9.1.3.5 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is
composed of several consecutive pages, and each lock region has its associated lock bit.
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC
triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.6 Security Bit Feature
The SAM3S8/SD8 features a security bit, based on a specific General Purpose NVM bit
(GPNVM bit 0). When the security is enabled, any access to the Flash, SRAM, Core Registers
and Internal Peripherals either through the ICE interface or through the Fast Flash Programming
Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of
the EEFC User Interface. Disabling the security bit can only be achieved by asserting the
ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated,
all accesses to the Flash, SRAM, Core registers, Internal Peripherals are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
9.1.3.7 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are
factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal-
ibration bits.
9.1.3.8 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the unique identifier.
9.1.3.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program-
ming with market-standard industrial programmers.
Table 9-1. Lock bit number
Product Number of lock bits Lock region size
SAM3S8/SD8 16 32 kbytes (128 pages)
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SAM3S8/SD8 Summary
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
9.1.3.10 SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is
set to 0.
9.1.3.11 GPNVM Bits
The SAM3S8 features two GPNVM bits, whereas SAM3SD8 features three GPNVM bits. These
bits can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set
GPNVM Bit” of the EEFC User Interface.
The Flash of the SAM3S8 is composed of 512 Kbytes in a single bank, while the SAM3SD8
Flash is composed of dual banks, each containing 256 Kbytes. The dual-bank function enables
programming one bank while the other one is read (typically while the application code is run-
ning). Only one EEFC (Flash controller) controls the two banks. Note that it is not possible to
program simultaneously, or read simultaneously, the dual banks of the Flash.
The first bank of 256 Kbytes is called Bank 0 and the second bank of 256 Kbytes, Bank 1.
The SAM3SD8 embeds an additional GPNVM bit: GPNVM2.
9.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed via GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting
ERASE clears the GPNVM Bit 2 and thus selects the boot from bank 0 by default.
Table 9-2. General-purpose Non volatile Memory Bits
GPNVMBit[#] Function
0 Security bit
1 Boot mode selection
2 Bank selection (Bank 0 or Bank 1) Only on SAM3SD8

ATSAM3SD8BA-MU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
ARM Microcontrollers - MCU QFN,Grn, IT, MRL A
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