34
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell.
The zero-power power-on reset allows the Supply Controller to start properly, while the soft-
ware-programmable brownout detector allows detection of either a battery discharge or main
voltage loss.
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC
oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal
oscillator and select it as the Slow Clock source.
The Supply Controller starts up the device by sequentially enabling the internal power switches
and the Voltage Regulator, then it generates the proper reset signals to the core power supply.
It also enables to set the system in different low-power modes and to wake it up from a wide
range of events.
10.5 Clock Generator
The Clock Generator is made up of:
One Low-power 32768Hz Slow Clock Oscillator with bypass mode
One Low-power RC Oscillator
One 3-20 MHz Crystal Oscillator, which can be bypassed
One Fast RC Oscillator, factory programmed. Three output frequencies can be selected: 4, 8
or 12 MHz. By default 4 MHz is selected.
One 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
One 60 to 130 MHz programmable PLL (PLLA), provides the clock, MCK to the processor
and peripherals. The PLLA input frequency is from 3.5 MHz to 20 MHz.
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11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
Figure 10-2. Clock Generator Block Diagram
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
the Processor Clock, HCLK
the Free running processor clock, FCLK
the Cortex SysTick external clock
the Master Clock, MCK, in particular to the Matrix and the memory interfaces
the USB Clock, UDPCK
independent peripheral clocks, typically at the frequency of MCK
three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the fast RC oscillator running at
4 MHz.
The user can trim the 8 and 12 MHz RC Oscillator frequency by software.
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLL and
Divider A
PLLA Clock
PLLACK
12M Main
Oscillator
PLL and
Divider B
On Chip
32k RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
XTALSEL
PLLB Clock
PLLBCK
On Chip
12/8/4 MHz
RC OSC
MAINSEL
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11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
Figure 10-3. Power Management Controller Block Diagram
The SysTick calibration value is fixed at 8000, which allows the generation of a time base of 1
ms with SysTick clock at 8 MHz (max HCLK/8 = 64 MHz/8)
10.7 Watchdog Timer
16-bit key-protected only-once Programmable Counter
Windowed, prevents the processor to be in a deadlock on the watchdog access
10.8 SysTick Timer
24-bit down counter
Self-reload capability
Flexible System timer
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
HCK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLBCK
pck[..]
PLLBCK
PLLBCK
UDPCK
ON/OFF
ON/OFF
FCLK
SystTick
Divider
/8

ATSAM3SD8BA-MU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
ARM Microcontrollers - MCU QFN,Grn, IT, MRL A
Lifecycle:
New from this manufacturer.
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