5T93GL04PGGI8 Datasheet 5T93GL04PGGI, 5T93GL04PGGI8 | P1-P3

DATA SHEET

2.5V LVDS, 1:4 Glitchless Clock Buffer

TERABUFFER™ II

5T93GL04

General Description

The 5T93GL04 2.5V differential clock buffer is a user-selectable

differential input to four LVDS outputs. The fanout from a differential

input to four LVDS outputs reduces loading on the preceding driver

and provides an efficient clock distribution network. The 5T93GL04

can act as a translator from a differential HSTL, eHSTL, LVEPECL

(2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A

single-ended 3.3V / 2.5V LVTTL input can also be used to translate

to LVDS outputs. The redundant input capability allows for

glitchless change-over from a primary clock source to a secondary

clock source up to 450MHz. Selectable inputs are controlled by SEL.

During the switchover, the output will disable low for up to three clock

cycles of the previously-selected input clock. The outputs will remain

low for up to three clock cycles of the newly-selected clock, after

which the outputs will start from the newly-selected input. A FSEL

pin has been implemented to control the switchover in cases where

a clock source is absent or is driven to DC levels below the minimum

specifications.

The IDT5T93GL04 outputs can be asynchronously

enabled/disabled. When disabled, the outputs will drive to the value

selected by the GL pin. Multiple power and grounds reduce noise.

Applications

• Clock distribution

Features

• Guaranteed low skew: <50ps (maximum)

• Very low duty cycle distortion: <100ps (maximum

• High speed propagation delay: <2.2ns (maximum)

• Up to 450MHz operation

• Selectable inputs

• Hot insertable and over-voltage tolerant inputs

• 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL

(3.3V), CML or LVDS input interface

• Selectable differential inputs to four LVDS outputs

• Power-down mode

• At power-up, FSEL should be LOW

• 2.5V V

• -40°C to 85°C ambient operating temperature

• Available in TSSOP package

• Recommends IDT5T9304 if glitchless input selection is not

required

• Not Recommended for New Designs

• For functional replacement use 8SLVD1204

24-Lead TSSOP

4.4mm x 7.8mm x 1.0mm package body

G Package

Top View

Pin Assignment

GND

FSEL

SEL

GND

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016

Rev A 3/12/15 2 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II

5T93GL04 DATA SHEET

Block Diagram

SEL

OUTPUT

CONTROL

OUTPUT

CONTROL

FSEL

OUTPUT

CONTROL

OUTPUT

CONTROL

2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 3 Rev A 3/12/15

5T93GL04 DATA SHEET

Table 1. Pin Descriptions

NOTES:

1. Inputs are capable of translating the following interface standards:

Single-ended 3.3V and 2.5V LVTTL levels

Differential HSTL and eHSTL levels

Differential LVEPECL (2.5V) and LVPECL (3.3V) levels

Differential LVDS levels

Differential CML levels

2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control

signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry.

3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain

disabled until the device completes power-up after asserting PD.

4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is

no input signal.

Table 2. Pin Characteristics (TA = +25°C, F = 1.0MHz)

NOTE: This parameter is measured at characterization but not tested.

Function Tables

Name Type Description

A[1:2] Input Adjustable

(1, 4)

Clock input. A[1:2] is the "true" side of the differential clock input.

[1:2] Input Adjustable

(1, 4)

Complementary clock inputs. A[1:2] is the complementary side of A[1:2].

For LVTTL single-ended operation, A[1:2] should be set to the desired toggle voltage

for A[1:2]:

3.3V LVTTL V

REF = 1650mV

2.5V LVTTL V

REF = 1250mV

G Input LVTTL

Gate control for differential outputs Q1 and Q1

through Q4 and Q4. When G is LOW,

the differential outputs are active. When G

is HIGH, the differential outputs are

asynchronously driven to the level designated by GL

(2)

GL Input LVTTL

Specifies output disable level. If HIGH, "true" outputs disable HIGH and

"complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and

"complementary" outputs disable HIGH.

Q[1:2] Output LVDS Clock outputs.

Q[1:2] Output LVDS Complementary clock outputs.

SEL Input LVTTL

Reference clock select. When LOW, selects A2 and A2

When HIGH, selects A1 and A1

PD Input LVTTL

Power-down control. Shuts off entire chip. If LOW, the device goes into low power

mode. Inputs and outputs are disabled. Both “true” and "complementary" outputs will

pull to VDD. Set HIGH for normal operation.

(3)

FSEL Input LVTTL

At a rising edge, FSEL forces select to the input designated by SEL. Apply a

LOW-to-HIGH transition to force an input selection. Set to logic LOW level at startup

and if a forced input selection is not needed.

Power Power supply for the device core and inputs.

GND Power Ground.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Input Capacitance 3pF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

5T93GL04PGGI8

Mfr. #:

Buy 5T93GL04PGGI8

Manufacturer:

IDT

Description:

Clock Buffer 450 MHz 2.5V LVDS 1;4 Clk Buffer

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

5T93GL04PGGI8

5T93GL04PGGI8

Products related to this Datasheet