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5T93GL04PGGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Rev A 3/12/15 10 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
5T93GL04 DATA SHEET
Glitchless Output Operation with Switching Input Clock Selection
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays LOW
for up to three clock cycles of the new input clock. After this, the output starts with the rising edge of the new input clock.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
FSEL Operation for When Current Clock Dies
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this
happens, the SEL pin should be toggled and FSEL asserted in order to force selection of the new input clock. The output clock will start up
after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied LOW for systems that use only one input. If this is not possible, the user must guarantee that the
unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
A1 -A1
A2 -A2
SEL
Qn - Qn
+VDIF
VDIF =0
-V
DIF
+VDIF
VDIF =0
-V
DIF
VIH
VTHI
VIL
+VDIF
VDIF =0
-V
DIF
2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 11 Rev A 3/12/15
5T93GL04 DATA SHEET
FSEL Operation for When Opposite Clock Dies
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When
this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after a number
of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied LOW for systems that use only one input. If this is not possible, the user must guarantee that the
unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock.
2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with
the input clock selected by the SEL pin.
3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will
be driven LOW and will restart with the input clock selected by the SEL pin.
Rev A 3/12/15 12 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
5T93GL04 DATA SHEET
Power Down Timing
NOTE 1: It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain
disabled until the device completes power-up after asserting PD.
NOTE 2: The Power Down Timing diagram assumes that GL is HIGH.
NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to V
DD
. In the Power Down Timing diagram this is
shown when Qn/Qn goes to V
DIF
= 0.
G
Qn - Qn
+VDIF
VDIF=0
-V
DIF
+VDIF
VDIF=0
-V
DIF
+VDIF
VDIF=0
-V
DIF
PD
A1 -A1
A2 -A2
VTHI
VIH
VIL
VTHI
VIH
VIL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

5T93GL04PGGI8

Mfr. #:
Buy 5T93GL04PGGI8
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1;4 Clk Buffer
Lifecycle:
New from this manufacturer.
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