2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 7 Rev A 3/12/15
5T93GL04 DATA SHEET
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, T
A
= -40°C to 85°C
NOTE 1.The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the V
DIF (AC) specification under actual use conditions.
NOTE 2.A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an
automatic test equipment (ATE) environment. This device meets the VX Specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5D. LVDS Differential Input AC Characteristics, T
A
= -40°C to 85°C
NOTE 1.The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE)
environment. This device meets the V
DIF (AC) specification under actual use conditions.
NOTE 2.A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This
device meets the VX Specification under actual use conditions.
NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals.
NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5E. AC Differential Input Characteristics
(1)
, T
A
= -40°C to 85°C
NOTE 1.The output will not change state until the inputs have crossed and the minimum differential voltage range defined by V
DIF
has been
met or exceeded.
NOTE 2.V
DIF
specifies the minimum input voltage (V
TR
– V
CP
) required for switching where V
TR
is the “true” input level and V
CP
is the
“complement” input level. The AC differential voltage must be achieved to guarantee switching to a new state.
NOTE 3.IV
CM
specified the maximum allowable range of (V
TR
+ V
CP
) /2.
Symbol Parameter Maximum Units
V
DIF
Input Signal Swing
(1)
732 mV
V
X
Differential Input Cross Point Voltage
(2)
LVEPECL 1082 mV
LVPECL 1880 m
D
H
Duty Cycle 50 %
V
THI
Input Timing Measurement Reference Level
(3)
Crossing Point V
t
R
/ t
F
Input Signal Edge Rate
(4)
2V/ns
Symbol Parameter Maximum Units
V
DIF
Input Signal Swing
(1)
400 mV
V
X
Differential Input Cross Point Voltage
(2)
1.2 V
D
H
Duty Cycle 50 %
V
THI
Input Timing Measurement Reference Level
(3)
Crossing Point V
t
R
/ t
F
Input Signal Edge Rate
(4)
2V/ns
Symbol Parameter Minimum Typical Maximum Units
V
DIF
AC Differential Voltage
(2)
0.1 3.6 V
V
X
Differential Input Cross Point Voltage 0.05 V
DD
V
V
CM
Common Mode Input Voltage Range
(3)
0.05 V
DD
V
V
IN
Input Voltage -0.3 3.6 V
Rev A 3/12/15 8 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
5T93GL04 DATA SHEET
Table 5F. AC Characteristics
(1,5)
, T
A
= -40°C to 85°C
NOTE: Characterized at 300MHz, unless otherwise noted.
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup.
NOTE 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load
conditions on any one device.
NOTE 3. Skew measured is the difference between propagation delay times tp
HL
and tp
LH
of any differential output pair under identical input
and output interfaces, transitions and load conditions on any one device.
NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices,
given identical transitions and load conditions at identical V
DD levels and temperature.
NOTE 5. All parameters are tested with a 50% input duty cycle.
NOTE 6. Guaranteed by design but not production tested.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
tsk(o)
Same Device Output Pin-to-Pin Skew
(2)
50 ps
tsk(p) Pulse Skew
(3)
100 ps
tsk(pp) Part-to-Part Skew
(4)
300 ps
tp
LH
Propagation Delay, Low-to-High
A Crosspoint to Qn/Qn
Crosspoint
1.5 2.2 ns
tp
HL
Propagation Delay, High-to-Low 1.5 2.2 ns
fo Frequency Range
(6)
450 MHz
t
PGE
Output Gate Enable Crossing
VTHI-to-Qn/Qn
Crosspoint
3.5 ns
t
PGD
Output Gate Enable Crossing
VTHI-to-Qn/Qn
Crosspoint Driven to
GL Designated Level
3.5 ns
t
PWRDN
PD Crossing V
THI
-to-Qn = V
DD
,
Qn = V
DD
100 µS
t
PWRUP
Output Gate Disable Crossing V
THI
to
Qn/Qn Driven to Designated Level
100 µS
t
R
/ t
F
Output Rise/Fall Time
(6)
20% to 80% 100 500 ps
2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 9 Rev A 3/12/15
5T93GL04 DATA SHEET
Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
NOTE 1: Pulse skew is calculated using the following expression:
tsk(p) =
|tp
HL
– tp
LH
|
Note that the tp
HL
and tp
LH
shown above are not valid measurements for this calculation because they are not taken from the same pulse.
NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Endable Showing Runt Pulse Generation
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user’s responsibility to time the G
signal to avoid this problem.
tPLH
tPHL
tSK(O)
tSK(O)
Qn - Qn
Qm - Qm
+VDIF
VDIF =0
-V
DIF
+VDIF
VDIF =0
-V
DIF
A[1:2] -A[1:2]
+VDIF
VDIF =0
-V
DIF
1/fo
tPLH
GL
G
Qn - Qn
tPGD
tPGE
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF =0
-V
DIF
A[1:2] -A[1:2]
+VDIF
VDIF =0
-V
DIF

5T93GL04PGGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1;4 Clk Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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