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5T93GL04PGGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 13 Rev A 3/12/15
5T93GL04 DATA SHEET
Test Circuits and Conditions
Test Circuit for Differential Input
Table 6A. Differential Input Test Conditions
Test Circuit for DC Outputs and Power Down Tests
Symbol V
DD
= 2.5V ± 0.2V Unit
V
THI
Crossing of A and A V
VDD/2
D.U.T.
A
A
Pulse
Generator
~50
Transmission Line
~50
Transmission Line
VIN
VIN
-VDD/2
Scope
50
50
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator
RL
RL
VOS VOD
Rev A 3/12/15 14 2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II
5T93GL04 DATA SHEET
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
Table 6B. Differential Input Test Conditions
NOTE 1: Specifications only apply to “Normal Operations” test condition. The T
IA
/E
IA
specification load is for reference only.
NOTE 2: The scope inputs are assumed to have a 2pF load to ground. T
IA
/E
IA
– 644 specifies 5pF between the output pair.
With C
L
= 8pF, this gives the test circuit appropriate 5pF equivalent load.
Symbol V
DD
= 2.5V ± 0.2V Unit
C
L
0
(1)
pF
8
(1,2)
pF
R
L
50
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator
50
50
Z=50
Z=50
SCOPE
C
L
-VDD/2
CL
2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 15 Rev A 3/12/15
5T93GL04 DATA SHEET
Ordering Information
Table 7. Ordering Information
Device Type Package Process
XXXXX
XX
X
PGG
5T93GL04
-40°C to + 85°C (Industrial)
TSSOP - Green
2.5V LVDS 1:4 Glitchless Clock Buffer
Terabuffer™ II
I
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

5T93GL04PGGI8

Mfr. #:
Buy 5T93GL04PGGI8
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1;4 Clk Buffer
Lifecycle:
New from this manufacturer.
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