ADIS16203CCCZ Datasheet ADIS16203/PCBZ, ADIS16203CCCZ | P19-P21

ADIS16203

Rev. A | Page 18 of 28

SAMPLE PERIOD CONTROL

The output data variables within the ADIS16203 are sampled and

updated at a rate based upon the SMPL_TIME control register. The

sample period can be precisely controlled over more than a three-

decade range using a time base with two settings and a 7-bit binary

count. The use of a time base that varies with a ratio of 1:31 allows

for a more optimum resolution in the sample period than a straight

binary counter. This is reflected in Figure 29, where the frequency is

presented on a logarithmic scale.

Note that the sample period given is defined as the cumulative time

required to sample, process, and update all data output variables. The

data output variables are sampled as a group and in unison with one

another. Whatever update rate is selected for one signal, all output

data variables are updated at the same rate whether they are monitored

via the SPI or not.

For a sample period setting of less than 1098.9 µs (SMPL_TIME ≤

0x07), the overall power dissipation in the part rises by approx-

imately 300%.

256

1 10k

FREQUENCY (Hz)

SMPL_TIME VALUE

192

128

10 100 1k

06108-026

Figure 29. SMPL_TIME Values vs. Sample Frequency

SMPL_TIME Register Definition

Address Default

Format Access

0x37, 0x36 0x0008 N/A R/W

Default is valid only until the first register write cycle.

The data within this register is nonvolatile, allowing for data

recovery upon reset.

Table 16. SMPL_TIME Bit Descriptions

Bit Description

15:8 Not used.

ADC Time Base Control. The MSB and TMBS set the

time base of the acquisition system to 122.1 s when

SR7 = 0 vs. 3.784 ms when SR7 = 1.

6:0

ADC Sample Period Count. The lower seven bits, SP6

to SP0, represent a binary count that results in the

combined sample period of the ADC when added to

one and then multiplied by the time base. (The

combined sample period is the period required to

sample and update all seven data outputs.) The

minimum setting for the lower seven bits, SP6 to SP0,

is 0x01. The overall acquisition time can be varied

from 244.2 s to 15.51 ms in 122.1 s increments for

TMBS = 0 and from 7.57 ms to 481 ms in 3.784 ms

increments for TMBS = 1. This equates to the sample

rate varying from 4096 SPS to 64.5 SPS for TMBS = 0

and from 132 SPS to 2.08 SPS for TMBS = 1.

FILTERING CONTROL

The ADIS16203 uses two types of filters for the output data. The

INCL_OUT and INCL_180_OUT data outputs use a Bartlett

Window function, and the SUPPLY_OUT, AUX_ADC, and

TEMP_OUT data outputs use a standard moving-averaging

filter. The number of taps set by the AVG_CNT control register

establishes the frequency response. The number of taps can be

derived from the contents of AVG_CNT using the following

equation:

CNTAVG

The following equations characterize the expected behavior of

each filtering approach. Figure 30 and Figure 31 shows the

frequency responses of each filter approach.

Averaging:

(

)

()

tfN

××π×

sin

)(

Bartlett Window:

(

)

)(

fHfH

The primary difference in the frequency responses offered by

each approach lies in their side lobes, which are 13 dB better in

the Bartlett Windowing approach. The Bartlett Window filtering

has two times the latency of the moving average filter.

ADIS16203

Rev. A | Page 19 of 28

–60

FREQUENCY (Hz)

ATTENUATION (dB)

06108-034

10000

–20

–40

10 100 1000

AVG_CNT = 8

N = 256

AVG_CNT = 4

N = 16

AVG_CNT = 1

N = 2

CORE SENSOR

RESPONSE

Figure 30. INCL_OUT, INCL_180_OUT Filter Response

–60

FREQUENCY (Hz)

ATTENUATION (dB)

06108-035

10000

–20

–40

10 100 1000

AVG_CNT = 8

N = 256

AVG_CNT = 4

N = 16

AVG_CNT = 1

N = 2

Figure 31. SUPPLY_OUT, AUX_ADC, and TEMP_OUT Filter Response,

= 4096 SPS

AVG_CNT Register Definition

Address Default

Format Access

0x39, 0x38 0x0007 Binary R/W

Default is valid only until the first register write cycle.

The AVG_CNT register contains information that represents the

number of averages to be applied to the output data. The number of

averages can be calculated by powers of 2. The number of averages

can be set to 1, 2, 4, 8, 16, 32, 64, 128, or 256.

Table 17. AVG_CNT Bit Description

Bit Description

15:4 Not used

3:0 Data bits (maximum = 1000, or a decimal value of 8)

POWER-DOWN CONTROL

The ADIS16203 has the ability to power down for user-defined

amounts of time, using the SLP_CNT control register. The

amount of time specified by the SLP_CNT control register is

equal to the binary count of the 8-bit control word multiplied

by 0.5 sec. Therefore, the 255 codes cover an overall shutdown

period of 127.5 seconds. The SLP_CNT register is volatile and is

set to 0 upon both power-up and subsequent wake-ups from the

power-down period. By setting the SLP_CNT control register to

a nonzero state, the ADIS16203 automatically powers down

once the next sample period is completed and the data output

registers are updated.

Once the ADIS16203 is placed into power-down mode, it can

only return to normal operation by timing out, by a reset command

(using the

RST

hardware control line), or by cycling the power

applied to the part. Once awake, the data output registers can be

scanned to determine what the state of the output registers were

prior to powering down. Once the data is recovered, the device

can be powered down again by simply writing a nonzero value

to the SLP_CNT control register and starting the process over.

Once the power-down time is complete, the recovery time for

the ADIS16203 is approximately 2 ms. This recovery time is

implemented within the device to allow for recovery of the

ADC prior to performing the next data conversion. Note that

the ND data bit within the data output control registers is cleared

when the ADIS16203 is powered down. Likewise, the new data

hardware I/O line is placed into an inactive state prior to being

powered down. The DAC is placed into a power-down mode as

well, resulting in the DAC output dropping to 0 V during the

power-down period. All control register settings are retained

while powered down with the exception of the SLP_CNT

control register.

SLP_CNT Register Definition

Address Default

Format Access

0x3B, 0x3A 0x0000 Binary R/W

Default is valid only until the first register write cycle.

Table 18. SLP_CNT Bit Descriptions

Bit Description

15:8 Not used

7:0 Data bits

ADIS16203

Rev. A | Page 20 of 28

STATUS FEEDBACK

The status control register within the ADIS16203 is utilized in deter-

mining the present state of the device. The ability to monitor the device

becomes necessary when and if the ADIS16203 has registered an alarm

and/or error condition as indicated by the alarm enable (Bit 14) within

the output data registers.

STATUS Register Definition

Address Default

Format Access

0x3D, 0x3C 0x0000 N/A Read only

Default is valid only until the first register write cycle.

The STATUS control register contains the alarm/error flags that

indicate abnormal operating conditions. See Table 19 for each bit’s

definition. Bit 0 and Bit 1 will automatically clear when the power

supply is in the specified range of operation. Setting Bit 4 in the

COMMAND register clears all flags. The flags are set on a continuing

basis as long as the error or alarm conditions persist.

Table 19. STATUS Bit Descriptions

Bit Description

15:10 Not used

9 Alarm 2 Status

1: Active

0: Normal mode

8 Alarm 1 status

1: Active

0: Normal mode

7:6 Not used

5 Self Test Fail

1: Self-test failure

0: Self-test pass

3 SPI Communications Failure

1: Error condition

0: Normal mode

2 Control Register Update Failed

1: Error condition

0: Normal mode.

1 Power Supply Above 3.625 V

1: Error condition

0: Normal mode

0 Power Supply Below 2.975 V

1: Error condition

0: Normal mode

COMMAND CONTROL

The COMMAND control register is utilized in sending global

commands to the ADIS16203 device. Any one of the global

commands can be implemented by simply writing 1 to its

corresponding bit location. The command control register has

write-only capability and is volatile. Table 20 describes each of

these global commands.

COMMAND Register Definition

Address Default

Format Access

0x3F, 0x3E 0x0000 N/A Write only

Default is valid only until the first register write cycle.

Table 20. COMMAND Bit Descriptions

Bit Description

15:8 Not used.

7 Software Reset Command.

6:5 Not used.

4 Clear Status Register, once per activation

Manual Flash Update Command. This command is

utilized in updating all of the nonvolatile registers to

Flash. Once the command is initiated, the supply

voltage, VDD, must remain within specified limits for

50 ms to ensure proper update of the nonvolatile

registers to Flash.

Auxiliary DAC Latch Command. This command acts to

latch the AUX_DAC control register data into the

auxiliary DAC upon receipt of the command. This allows

for sequential loading of the upper and lower AUX_DAC

data bytes via the SPI without having the auxiliary DAC

transition into unwanted, intermediate states based

upon the individual AUX_DAC data bytes. Once the two

bytes of AUX_DAC are loaded, the DAC latch command

is initiated to move the data into the auxiliary DAC itself.

Factory Reset Command. This command allows the user

to reset the INCL_NULL register to its nominal setting

(0x0000) upon receipt of the command. Data within the

moving average filters is reset. As the manual Flash

command (COMMAND register, Bit 3), this command

stores all of the nonvolatile registers to Flash. Once the

command is initiated, the supply voltage, VDD, must

remain within specified limits for 50 ms to ensure

proper update of the nonvolatile registers to Flash.

Null Command. This command loads the inclination

offset register with a value that zeros out the inclination

and outputs. Useful as a single command to simulta-

neously zero the inclination outputs. As the manual

Flash command (COMMAND register, Bit 3), this command

stores all of the nonvolatile registers to Flash. Once the

command is initiated, the supply voltage, VDD, must

remain within specified limits for 50 ms to ensure

proper update of the nonvolatile registers to Flash.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

ADIS16203CCCZ

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Inclinometers IC 360 Degree Inclinometer

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ADIS16203CCCZ

ADIS16203CCCZ

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