ADIS16203
Rev. A | Page 21 of 28
MISCELLANEOUS CONTROL REGISTER
The MSC_CTRL control register governs the operation of several
miscellaneous features: using the general purpose I/O for data-ready
(DR) hardware I/O function, reversing the polarity of rotation
(clockwise vs. counter clockwise), and self-test. The control bits for
each of these functions are described in Table 21 .
The operation of the data-ready hardware I/O function is very similar to
the alarm hardware I/O function (controlled through the ALM_CTRL
control register). In this case, the MSC_CTRL register can be used in
setting up one of the GPIO pins to serve as the hardware output pin
that indicates when the sampling, conversion, and processing of the
data output variables have been completed. This register provides
the ability to enable the data-ready hardware function and establish
its polarity.
The data-ready hardware I/O pin is reset automatically to an inactive
state part way through the next conversion cycle, resulting in a pulse
train with a duty cycle varying from ~15% to 35%, depending upon
the sample period setting. Upon completion of the next data processing
cycle, the data ready hardware I/O line is set to 1.
The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control registers
can influence the same GPIO pins. A priority level has been established
to avoid conflicting assignments of the two GPIO pins. This priority
level is defined as MSC_CTRL and has precedence over ALM_CTRL,
which has precedence over GPIO_CTRL.
The self-test operation exercises the base accelerometer’s mechanical
structure and establishes a mechanical diagnostic test. The self-test
offers the ability to have the ADIS16203 run an internal diagnostic
test, which returns a pass/fail condition (see the STATUS register
definition of Bit 5 in Table 19). This feature also provides the ability
to observe the incline angle outputs during the self-test function,
which is nominally 37°, regardless of the incline angle of the device.
Note that a self-test changes the contents of SMPL_TIME to improve
the speed of this test. Upon completion, the ADIS16203 restores the
original contents to SMPL_TIME.
MSC_CTRL Register Definition
Address Default
1
Format Access
0x35, 0x34 0x0000 N/A R/W
1
Default is valid only until the first register write cycle.
The 16-bit miscellaneous control register is used in the controlling
of the self-test and data-ready hardware functions. This includes
turning on and off the self-test function, as well as configuring
the data-ready function. For the data-ready function, the written
values are nonvolatile, allowing for data recovery upon reset.
The self-test data is volatile and is set to 0s upon reset. This
register has read/write capability.
Table 21. MSC_CTRL Bit Descriptions
Bit Description
15:11 Not used
10 No Self-Test on Power-Up
1: No self-test on power-up or reset
0: Self-test on power-up enabled (typically requires
approximately 13 ms in high performance mode and
approximately 35 ms in low power mode with every
power-up or reset)
9 Reverse Rotation
1: Reverses rotation of both inclination outputs
0: Normal operation
8 Self-Test Enable
1: ST enabled (continuous self-test)
0: ST disabled
7:3 Not used
2 Data-Ready Enable
1: DR enabled
0: DR disabled
1 Data-Ready Polarity
1: Active high
0: Active low
0 Data-Ready Line Select
1: DIO1
0: DIO0
ADIS16203
Rev. A | Page 22 of 28
PERIPHERALS
AUXILIARY ADC FUNCTION
The auxiliary ADC function integrates a standard 12-bit ADC
into the ADIS16203 to digitize other system-level analog signals.
The output of the ADC can be monitored through the AUX_ADC
control register, as defined in Table 6. The ADC consists of a 12-bit
successive approximation converter. The output data is presented in
straight binary format with the full-scale range extending from 0 V
to VREF. A high precision, low drift, factory-calibrated 2.5 V reference
is also provided.
Figure 32 shows the equivalent circuit of the analog input structure
of the ADC. The input capacitor, C1, is typically 4 pF and can be
attributed to parasitic package capacitance. The two diodes provide
ESD protection for the analog input. Care must be taken to ensure
that the analog input signals never exceed the supply rails by more
than 300 mV. This would cause these diodes to become forward-biased
and to start conducting. These diodes can handle 10 mA without
causing irreversible damage to the part. The resistor is a lumped
component that represents the on resistance of the switches. The
value of this resistance is typically 100 . Capacitor C2 represents
the ADC sampling capacitor and is typically 16 pF.
C2
C1
R1
V
DD
D
D
06108-028
Figure 32. Equivalent Analog Input Circuit
Conversion Phase: Switch Open
Track Phase: Switch Closed
For ac applications, removing high frequency components from the
analog input signal is recommended through the use of an RC low-
pass filter on the relevant analog input pins.
In applications where harmonic distortion and signal-to-noise ratio
are critical, the analog input should be driven from a low impedance
source. Large source impedances significantly affect the ac performance
of the ADC. This can necessitate the use of an input buffer amplifier.
When no input amplifier is used to drive the analog input, the source
impedance should be limited to values less than 1 k. The maximum
source impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated.
AUXILIARY DAC FUNCTION
The auxiliary DAC function integrates a standard 12-bit DAC
into the ADIS16203. The DAC output is buffered and fed off-chip
to allow for the control of miscellaneous system-level functions.
Data downloads through the writing of two adjacent data bytes
as defined in its register definition. To prevent the DAC from
transitioning through inadvertent states during data downloads,
a single command is used to simultaneously latch both data bytes
into the DAC after they have been written into the AUX_DAC
control register. This command is implemented by writing 1 to
Bit 2 of the command control register and, once received, results in
the DAC output transitioning to the desired state.
The DAC output provides an output range of 0 V to 2.5 V. The
DAC output buffer features a true rail-to-rail output stage. This
means that, unloaded, the output is capable of reaching within
5 mV of ground. Moreover, the DACs linearity performance
(when driving a 5 k resistive load to ground) is good through
the full transfer function, except for Code 0 to Code 100. Linearity
degradation near ground is caused by saturation of the output
amplifier. As the output is forced to sink more current, the non-
linear region at the bottom of the transfer function becomes
larger. Larger current demands can significantly limit output
voltage swing.
AUX_DAC Register Definition
Address Default
1
Format Access
0x31, 0x30 0x0000 Binary R/W
1
Default is valid only until the first register write cycle.
The AUX_DAC register controls the DAC function of the
ADIS16203. The data bits provide a 12-bit binary format number,
with 0 representing 0 V and 0x0FFFh representing 2.5 V. The
data within this register is volatile and is set to 0s upon reset.
This register has read/write capability.
Table 22. AUX_DAC Bit Descriptions
Bit Description
15:12 Not used
11:0 Data bits
ADIS16203
Rev. A | Page 23 of 28
GENERAL-PURPOSE I/O CONTROL
As previously noted, the ADIS16203 provides two general-purpose,
bidirectional I/O pins (GPIOs) that are available to the user for control
of auxiliary circuits within the target application. All I/O pins are 5 V
tolerant, meaning that the GPIOs support an input voltage of 5 V. Each
GPIO pin has an internal pull-up resistor of approximately 100 k
and a drive capability of 1.6 mA. The direction, as well as the logic
level, can be controlled for these GPIO pins through the GPIO_CTRL
control register, as defined in Table 23.
These same GPIO pins are also controllable through the ALM_CTRL
and MSC_CTRL control registers. The priority for these three control
registers in controlling the two GPIO pins is MSC_CTRL has prece-
dence over ALM_CTRL, which has precedence over GPIO_CTRL.
GPIO_CTRL Register Definition
Address Default
1
Format Access
0x33, 0x32 0x0000 N/A R/W
1
Default is valid only until the first register write cycle.
The data within the general-purpose digital I/O control register is
volatile and is set to 0s upon reset.
Table 23. GPIO_CTRL Bit Descriptions
Bit Description
15:10 Not used
9 General-Purpose I/O Line 1 Polarity
0: Low
1: High
8 General-Purpose I/O Line 0 Polarity
0: Low
1: High
7:2 Not used
1 General-Purpose I/O Line 1, Data Direction Control
0: Input
1: Output
0 General-Purpose I/O Line 0, Data Direction Control
0: Input
1: Output

ADIS16203CCCZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Inclinometers IC 360 Degree Inclinometer
Lifecycle:
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