ADIS16203
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
T
A
= +25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2.
Parameter Description Min
1
Typ Max Unit
f
SCLK
Fast mode, SMPL_TIME ≤ 0x07 (f
S
≥ 1024 Hz) 0.01 2.5 MHz
Normal mode, SMPL_TIME ≥ 0x08 (f
S
≤ 910 Hz) 0.01 1.0 MHz
t
DATARATE
Chip select period, fast mode, SMPL_TIME ≤ 0x07 (f
S
≥ 1024 Hz) 40 s
Chip select period, normal mode, SMPL_TIME ≥ 0x08 (f
S
≤ 910 Hz) 100 s
t
CS
Chip select to clock edge 48.8 ns
t
DAV
Data output valid after SCLK falling edge
2
100 ns
t
DSU
Data input setup time before SCLK rising edge 24.4 ns
t
DHD
Data input hold time after SCLK rising edge 48.8 ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SFS
CS
high after SCLK edge
3
5 ns
1
Guaranteed by design, not production tested.
2
The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of
CS
. The rest of the DOUT bits are clocked after the falling edge of SCLK and are
governed by this specification.
3
This parameter may need to be expanded to allow for proper capture of the LSB. After
CS
goes high, the DOUT line goes into a high impedance state.
TIMING DIAGRAMS
CS
SCLK
t
DATARATE
t
STALL
=
t
DATARATE
– 16/
f
SCLK
t
STALL
06108-002
Figure 2. SPI Chip Select Timing
CS
SCLK
DOUT
DIN
1 2 3 4 5 6 15 16
W/R A5 A4 A3 A2
D2
MSB DB14
D1 LSB
DB13 DB12 DB10DB11 DB2 LSBDB1
t
CS
t
SFS
t
DAV
t
DHD
t
DSU
06108-003
Figure 3. SPI Timing, Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1
