AD7273/AD7274
Rev. 0 | Page 13 of 28
18000
0
2045
CODE
NUMBER OF CODES
16000
14000
12000
10000
8000
6000
4000
2000
2046 2047 2048 2049 2050
30,000 CODES
04973-022
Figure 22. Histogram of Codes for 30,000 Samples
12.0
10.0
1.4 3.6
V
REF
(V)
EFFECTIVE NUMBERS OF BITS
04973-023
11.5
11.0
10.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
Figure 23. ENOB/SINAD vs. Reference Voltage
AD7273/AD7274
Rev. 0 | Page 14 of 28
TERMINOLOGY
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7273/
AD7274, the endpoints of the transfer function are zero scale at
0.5 LSB below the first code transition and full scale at 0.5 LSB
above the last code transition.
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00 . . . 000) to (00 . . .
001) from the ideal, that is, AGND + 0.5 LSB.
Gain Error
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal, that is, VREF – 1.5 LSB, after
adjusting for the offset error.
Tota l Unadjuste d Error ( TUE)
A comprehensive specification that includes gain, linearity, and
offset errors.
Track-and-Hold Acquisition Time
The time required for the output of the track-and-hold amplifier
to reach its final value, within ±0.5 LSB, after the end of the
conversion. See the
Serial Interface section for more details.
Signal-to-Noise + Distortion Ratio (SINAD)
The measured ratio of signal to noise plus distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental, and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), including
harmonics but excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process: the
more levels, the smaller the quantization noise. For an ideal N-bit
converter, the SINAD is
dB76.102.6 += NSINAD
According to this equation, the SINAD is 74 dB for a 12-bit
converter and 62 dB for a 10-bit converter. However, various
error sources in the ADC, including integral and differential
nonlinearities and internal ac noise sources, cause the measured
SINAD to be less than its theoretical value.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. It is
defined as:
()
1
2
6
2
5
2
4
2
3
2
2
log20dB
V
VVVVV
THD
++++
=
where
V
1
is the rms amplitude of the fundamental, and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to f /2, excluding dc) to the rms value
of the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum; however,
for ADCs with harmonics buried in the noise floor, it is deter-
mined by a noise peak.
S
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m and
n = 0, 1, 2, 3, …. Intermodulation distortion terms are those for
which neither m nor n are equal to zero. For example, the second-
order terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The AD7273/AD7274 are tested using the CCIF standard in
which two input frequencies are used (see fa and fb in the
Specifications section). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, and
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC V supply of frequency f .
DD S
(
)
(
)
S
PfPfPSRR log10dB
=
where
Pf is the power at frequency f in the ADC output; Pf
S
is
the power at frequency
f
S
coupled onto the ADC V
DD
supply.
Aperture Delay
The measured interval between the leading edge of the sampling
clock and the point at which the ADC actually takes the sample.
Aperture Jitter
The sample-to-sample variation in the effective point in time at
which the sample is taken.
AD7273/AD7274
Rev. 0 | Page 15 of 28
CIRCUIT INFORMATION
The AD7273/AD7274 are high speed, low power, 10-/12-bit,
single supply ADCs, respectively. The parts can be operated
from a 2.35 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7273/AD7274 are capable of
throughput rates of 3 MSPS when provided with a 48 MHz clock.
The AD7273/AD7274 provide the user with an on-chip track-
and-hold ADC and a serial interface housed in an 8-lead TSOT
or an 8-lead MSOP package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part and provides the clock
source for the successive approximation ADC. The analog input
range is 0 to V
REF
. An external reference in the range of 1.4 V to
V
DD
is required by the ADC.
The AD7273/AD7274 also feature a power-down option to save
power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the
Modes of Operation section.
CONVERTER OPERATION
The AD7273/AD7274 are successive approximation ADCs
based on a charge redistribution DAC.
Figure 24 and Figure 25
show simplified schematics of the ADC.
Figure 24 shows the
ADC during its acquisition phase, where SW2 is closed, SW1 is
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor acquires the signal on V
IN
.
COMPARATOR
ACQUISITION
PHASE
V
DD
/2
SW2
V
IN
SAMPLING
CAPACITOR
AGND
A
SW1
B
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
04973-024
Figure 24. ADC Acquisition Phase
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(see
Figure 25). The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Figure 26 shows the ADC transfer function.
COMPARATOR
ACQUISITION
PHASE
V
DD
/2
SW2
V
IN
SAMPLING
CAPACITOR
AGND
A
SW1
B
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
04973-025
Figure 25. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7273/AD7274 is straight binary.
The designed code transitions occur midway between
successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The
LSB size is V
REF
/4,096 for the AD7274 and V
REF
/1,024 for the
AD7273. The ideal transfer characteristic for the
AD7273/AD7274 is shown in
Figure 26.
000...000
0V
ADC CODE
ANALOG INPUT
111...111
000...001
111...000
011...111
111...110
000...010
1LSB = V
REF
/4096 (AD7274)
1LSB = V
REF
/1024 (AD7273)
+V
REF
– 1.5LSB0.5LSB
04973-026
Figure 26. AD7273/AD7274 Transfer Characteristic

AD7274BRMZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12Bit 3MSPS SAR IC
Lifecycle:
New from this manufacturer.
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