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AD7274BRMZ

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AD7273/AD7274
Rev. 0 | Page 7 of 28
TIMING SPECIFICATIONS
V
DD
= 2.35 V to 3.6 V; V
REF
= 2.35 to V
DD
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Guaranteed by characterization. All input signals
are specified with tr = tf = 2 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 4.
Parameter
Limit at T
MIN
, T
MAX
AD7273/AD7274
Unit Description
f
SCLK
2
500 kHz min
3
48 MHz max
t
CONVERT
14 × t
SCLK
AD7274
12 × t
SCLK
AD7273
t
QUIET
4 ns min
Minimum quiet time required between bus relinquish and start of
next conversion
t
1
3 ns min
Minimum
CS pulse width
t
2
6 ns min
CS to SCLK setup time
t
3
4
4 ns max
Delay from
CS until SDATA three-state disabled
t
4
4
15 ns max Data access time after SCLK falling edge
t
5
0.4 t
SCLK
ns min SCLK low pulse width
t
6
0.4 t
SCLK
ns min SCLK high pulse width
t
7
4
5 ns min SCLK to data valid hold time
t
8
14 ns max SCLK falling edge to SDATA three-state
5 ns min SCLK falling edge to SDATA three-state
t
9
4.2 ns max
CS rising edge to SDATA three-state
t
POWER-UP
5
1 μs max Power-up time from full power-down
1
Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum f
SCLK
at which specifications are guaranteed.
4
The time required for the output to cross the V
IH
or V
IL
voltage.
5
See the Power-Up Times section
SCLK
V
IH
V
IL
SDATA
t
4
04973-002
Figure 2. Access Time After SCLK Falling Edge
SCLK
V
IH
V
IL
SDATA
t
7
04973-003
Figure 3. Hold Time After SCLK Falling Edge
SCLK
1.4V
SDATA
t
8
04973-004
Figure 4. SCLK Falling Edge SDATA Three-State
AD7273/AD7274
Rev. 0 | Page 8 of 28
TIMING EXAMPLES
For the AD7274, if
CS
is brought high during the 14
th
SCLK
rising edge after the two leading zeros and 12 bits of the
conversion are provided, the part can achieve the fastest
throughput rate, 3 MSPS. If
CS
is brought high during the 16
th
SCLK rising edge after the two leading zeros, 12 bits of the
conversion, and two trailing zeros are provided, a throughput
rate of 2.97 MSPS is achievable. This is illustrated in the
following two timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, f
SCLK
= 48 MHz, and
the throughput is 3 MSPS. This produces a cycle time of
t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 333 ns, where t
2
= 6 ns min and
t
ACQ
= 67 ns. This satisfies the requirement of 60 ns for t
ACQ
.
Figure 6 also shows that t
ACQ
comprises 0.5(1/f
SCLK
) + t
9
+ t
QUIET
,
where t
9
= 4.2 ns max. This allows a value of 52.8 ns for t
QUIET
,
satisfying the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, f
SCLK
= 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time
of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 336 ns, where t
2
= 6 ns min and
t
ACQ
= 70 ns. Figure 7 shows that t
ACQ
comprises 2.5(1/f
SCLK
) +
t
8
+ t
QUIET
, where t
8
= 14 ns max. This satisfies the minimum
requirement of 4 ns for t
QUIET.
12345 13141516
SCLK
S
DAT
A
THREE-STATETHREE-
STATE
TWO LEADING
ZEROS
TWO TRAILING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0 ZERO ZERO
t
6
t
5
t
8
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
04973-005
Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle
12345 1314
SCLK
S
DAT
A
THREE-STATETHREE-
STATE
TWO LEADING
ZEROS
B
CS
t
3
t
CONVERT
t
2
ZEROZ DB11 DB10 DB9 DB1 DB0
t
6
t
9
t
1
t
QUIET
1/THROUGHPUT
t
4
t
7
04973-006
t
5
Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle
12345 1312 14 15 16
SCLK
B
CS
t
CONVERT
t
2
t
8
t
1
t
QUIET
1/THROUGHPUT
12.5(1/f
SCLK
)
t
ACQUISITION
04973-007
Figure 7. Serial Interface Timing 16 SCLK Cycle
AD7273/AD7274
Rev. 0 | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 5.
Parameters Ratings
V
DD
to AGND/DGND −0.3 V to +6 V
Analog Input Voltage to AGND −0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND −0.3 V to +6 V
Digital Output Voltage to DGND −0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
1
±10 mA
Operating Temperature Range
Commercial (B Grade) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
6-Lead TSOT Package
θ
JA
Thermal Impedance 230°C/W
θ
JC
Thermal Impedance 92°C/W
8-Lead MSOP Package
θ
JA
Thermal Impedance 205.9°C/W
θ
JC
Thermal Impedance 43.74°C/W
Lead Temperature Soldering
Reflow (10 to 30 sec) 255°C
Lead Temperature Soldering
Reflow (10 to 30 sec) 260°C
ESD 1.5 kV
1
Transient currents of up to 100 mA cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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AD7274BRMZ

Mfr. #:
Buy AD7274BRMZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12Bit 3MSPS SAR IC
Lifecycle:
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