AD7274BRMZ Datasheet AD7274BRMZ-REEL, AD7274BRMZ, AD7273BUJZ-500RL7 | P16-P18

AD7273/AD7274

Rev. 0 | Page 16 of 28

TYPICAL CONNECTION DIAGRAM

Figure 27 shows a typical connection diagram for the AD7273/

AD7274. An external reference must be applied to the ADC.

This reference can be in the range of 1.4 V to V

. A precision

reference, such as the REF19x family or the ADR421, can be

used to supply the reference voltage to the AD7273/AD7274.

The conversion result is output in a 16-bit word with two leading

zeros followed by the 12-bit or 10-bit result. The 12-bit result from

the AD7274 is followed by two trailing zeros, and the 10-bit result

from the AD7273 is followed by four trailing zeros.

Table 7 provides some typical performance data with various

references under the same setup conditions for the AD7274.

Table 7. AD7274 Performance (Various Voltage Reference IC)

Voltage Reference

AD7274 SNR Performance

1 MHz Input

AD780 @ 2.5 V 71.3 dB

AD780 @ 3 V 70.1 dB

REF195 70.9 dB

AD7273/

AD7274

SERIAL

INTERFACE

0V TO V

REF

INPUT

DSP/

REF

AGND/DGND

SCLK

SDATA

0.1

F 10

10pF 0.1

2.5V

3.6V

SUPPLY

4.6 mA

REF195

04973-027

Figure 27. AD7273/AD7274 Typical Connection Diagram

ANALOG INPUT

Figure 28 shows an equivalent circuit of the analog input

structure of the AD7273/AD7274. The two diodes, D1 and D2,

provide ESD protection for the analog inputs. Care must be

taken to ensure that the analog input signal never exceeds the

supply rails by more than 300 mV. Signals exceeding this value

cause these diodes to become forward biased and to start

conducting current into the substrate. These diodes can

conduct a maximum current of 10 mA without causing

irreversible damage to the part. Capacitor C1 in

Figure 28 is

typically about 4 pF and can primarily be attributed to pin

capacitance. Resistor R1 is a lumped component made up of the

on resistance of a switch. This resistor is typically about 75 Ω.

Capacitor C2 is the ADC sampling capacitor and has a capacitance

of 32 pF typically. For ac applications, removing high frequency

components from the analog input signal is recommended by

using a band-pass filter on the relevant analog input pin. In

applications where harmonic distortion and signal-to-noise

ratio are critical, the analog input should be driven from a low

impedance source. Large source impedances significantly affect

the ac performance of the ADCs. This may necessitate the use

of an input buffer amplifier. The AD8021 op amp is compatible

with this device; however, the choice of the op amp is a function

of the particular application.

4pF

CONVERSION PHASE–SWITCH OPEN

TRACK PHASE–SWITCH CLOSED

04973-028

Figure 28. Equivalent Analog Input Circuit

When no amplifier is used to drive the analog input, the source

impedance should be limited to a low value. The maximum source

impedance depends on the amount of THD that can be tolerated.

The THD increases as the source impedance increases and perfor-

mance degrades.

Figure 14 shows a graph of the THD vs. the

analog input frequency for different source impedances when

using a supply voltage of 3 V and sampling at a rate of 3 MSPS.

DIGITAL INPUTS

The digital inputs applied to the AD7273/AD7274 are not

limited by the maximum ratings that limit the analog inputs.

Instead, the digital inputs can be applied at up to 6 V and are

not restricted by the V

+ 0.3 V limit of the analog inputs. For

example, if the AD7273/AD7274 were operated with a V

3 V, then 5 V logic levels could be used on the digital inputs.

However, it is important to note that the data output on SDATA

still has 3 V logic levels when V

= 3 V. Another advantage of

SCLK and

not being restricted by the V

+ 0.3 V limit is

that power supply sequencing issues are avoided. For example,

unlike with the analog inputs, with the digital inputs, if

SCLK are applied before V

, there is no risk of latch-up.

AD7273/AD7274

Rev. 0 | Page 17 of 28

MODES OF OPERATION

The mode of operation of the AD7273/AD7274 is selected by

controlling the logic state of the

signal during a conversion.

There are three possible modes of operation: normal mode,

partial power-down mode, and full power-down mode. The

point at which

is pulled high after the conversion is initiated

determines which power-down mode, if any, the device enters.

Similarly, if the device is already in power-down mode,

can

control whether the device returns to normal operation or

remains in power-down mode. These modes of operation are

designed to provide flexible power management options, which

can be chosen to optimize the power dissipation/throughput

rate ratio for different application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance

because the AD7273/AD7274 remain fully powered at all times,

eliminating worry about power-up times. Figure 29 shows the

general diagram of the operation of the AD7273/AD7274 in

this mode.

The conversion is initiated on the falling edge of

as described

in the Serial Interface section. To ensure that the part remains

fully powered up at all times,

must remain low until at least

10 SCLK falling edges elapse after the falling edge of

. If

brought high any time after the 10

SCLK falling, but before the

SCLK falling edge, the part remains powered up, but the

conversion is terminated, and SDATA goes back into three-state.

For the AD7274, a minimum of 14 serial clock cycles are

required to complete the conversion and access the complete

conversion result. For the AD7273, a minimum of 12 serial

clock cycles are required to complete the conversion and access

the complete conversion result.

can idle high until the next conversion or low until

returns high before the next conversion (effectively idling

low). Once a data transfer is complete (SDATA has returned to

three-state), another conversion can be initiated after the quiet

time, t

QUIET

, has elapsed by bringing

low again.

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. An example of this is when either

the ADC is powered down between each conversion or a series

of conversions is performed at a high throughput rate and then

the ADC is powered down for a relatively long duration between

these bursts of several conversions.

When the AD7273/AD7274 are in partial power-down mode,

all analog circuitry is powered down except the bias generation

circuit.

To enter partial power-down mode, interrupt the conversion

process by bringing

high between the second and 10

falling

edges of SCLK, as shown in

Figure 30. Once

is brought high

in this window of SCLKs, the part enters partial power-down

mode, the conversion that was initiated by the falling edge of

is terminated, and SDATA goes back into three-state. If

is brought high before the second SCLK falling edge, the part

remains in normal mode and does not power down. This prevents

accidental power-down due to glitches on the

line.

To exit this mode of operation and power up the AD7274/

AD7273, perform a dummy conversion. On the falling edge of

, the device begins to power up and continues to power up as

long as

is held low until after the falling edge of the 10

SCLK.

The device is fully powered up once 16 SCLKs elapse; valid data

results from the next conversion, as shown in

Figure 31. If

brought high before the 10

falling edge of SCLK, the AD7274/

AD7273 goes into full power-down mode. Therefore, although

the device may begin to power up on the falling edge of

, it

powers down on the rising edge of

as long as this occurs

before the 10

SCLK falling edge.

If the AD7273/AD7274 is already in partial power-down mode

and

is brought high before the 10

falling edges of SCLK, the

device enters full power-down mode. For more information on

the power-up times associated with partial power-down mode

in various configurations, see the

Power-Up Times section.

FULL POWER-DOWN MODE

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, because power-up from a full power-down takes

substantially longer than that from a partial power-down. This

mode is suited to applications where a series of conversions

performed at a relatively high throughput rate are followed by

a long period of inactivity and thus power-down.

When the AD7273/AD7274 are in full power-down mode, all

analog circuitry is powered down. To enter full power-down

mode put the device into partial power-down mode by bringing

high between the second and 10

falling edges of SCLK. In

the next conversion cycle, interrupt the conversion process in

the way shown in

Figure 32 by bringing

high before the 10

SCLK falling edge. Once

is brought high in this window of

SCLKs, the part powers down completely. Note that it is not

necessary to complete 16 SCLKs once

is brought high to enter

either of the power-down modes. Glitch protection is not

available when entering full power-down mode.

To exit full power-down mode and power up the AD7273/

AD7274 again, perform a dummy conversion, similar to when

powering up from partial power-down mode. On the falling

AD7273/AD7274

Rev. 0 | Page 18 of 28

edge of

, the device begins to power up and continues to

power up until after the falling edge of the 10

SCLK as long as

is held low. The power-up time required must elapse before

a conversion can be initiated, as shown in

Figure 33. See the

Power-Up Times section for the power-up times associated with

the AD7273/AD7274.

POWER-UP TIMES

The AD7273/AD7274 has two power-down modes, partial

power-down and full power-down, which are described in

detail in the Modes of Operation section. This section deals

with the power-up time required when coming out of either of

these modes.

To power up from partial power-down mode, one cycle is

required. Therefore, with a SCLK frequency of up to 48 MHz,

one dummy cycle is sufficient to allow the device to power up

from partial power-down mode. Once the dummy cycle is

complete, the ADC is fully powered up and the input signal is

acquired properly. The quiet time, t

QUIET

, must be allowed from

the point where the bus goes back into three-state after the

dummy conversion to the next falling edge of

To power up from full power-down, approximately 1 s should

be allowed from the falling edge of

, shown in Figure 33 as

POWER-UP

. Note that during power-up from partial power-down

mode, the track-and-hold, which is in hold mode while the part

is powered down, returns to track mode after the first SCLK

edge is received after the falling edge of

. This is shown as

Point A in

Figure 31.

When power supplies are first applied to the AD7273/AD7274,

the ADC can power up in either of the power-down modes or

in normal mode. Because of this, it is best to allow a dummy

cycle to elapse to ensure that the part is fully powered up before

attempting a valid conversion. Likewise, if the part is to be kept

in partial power-down mode immediately after the supplies are

applied, two dummy cycles must be initiated. The first dummy

cycle must hold

low until after the 10

SCLK falling edge

(see

Figure 29). In the second cycle,

must be brought high

between the second and 10

SCLK falling edges (see Figure 30).

Alternatively, if the part is to be placed into full power-down

mode after the supplies are applied, three dummy cycles must

be initiated. The first dummy cycle must hold

low until after

the 10

SCLK falling edge (see Figure 29); the second and third

dummy cycles place the part into full power-down mode (see

Figure 32). See also the Modes of Operation section.

SCLK

110121416

AD7273/AD7674

SDATA VALID DATA

04973-029

Figure 29. Normal Mode Operation

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AD7274BRMZ

Mfr. #:

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Manufacturer:

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Description:

Analog to Digital Converters - ADC 12Bit 3MSPS SAR IC

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AD7274BRMZ

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