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ADP3190AJRUZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
6-Bit, Programmable 2-/3-/4-Phase,
Synchronous Buck Controller
ADP3190
©2008 SCILLC. All rights reserved. Publication Order Number:
January 2008 – Rev. 2 ADP3190/D
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
±9.5 mV worst-case differential sensing error
over temperature
Logic-level PWM outputs for interface to external
high power drivers
PWM Flex-Mode
TM
architecture for excellent load
transient performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
6-bit, digitally programmable 0.8375 V to 1.6 V output
Programmable short circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next generation Intel® processors
VRM modules
Game consoles
GENERAL DESCRIPTION
The ADP3190
1
is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
5 V (ADP3190A) or 12 V (ADP3190) main supply into the core
supply voltage required by high performance Intel processors.
The part uses an internal 6-bit DAC to read a voltage identifica-
tion (VID) code directly from the processor, which is used to
set the output voltage between 0.8375 V and 1.6 V. The devices
use a multimode PWM architecture to drive the logic-level
outputs at a programmable switching frequency that can be
optimized for VR size and efficiency. The phase relationship of
the output signals can be programmed to provide 2-, 3-, or 4-
phase operation, allowing for the construction of up to four
complementary buck switching stages.
The ADP3190 includes programmable, no-load offset and slope
functions to adjust the output voltage as a function of the load
current, so it is always optimally positioned for a system
transient. The ADP3190 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power-good output that accommodates on-the-fly
output voltage changes requested by the CPU.
FUNCTIONAL BLOCK DIAGRAM
V
C
C
PRECISION
REFERENCE
SOFT
START
DELAY
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
GND
ADP3190
DELAY
ILIMIT
PWRGD
RTRAMPADJ
PWM2
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
COMP
VID
DAC
DAC
+150mV
DAC
–250mV
CSREF
EN
CURRENT
LIMIT
CIRCUIT
CROWBAR CURRENT
LIMIT
CMP
CMP
CURRENT
BALANCING
CIRCUIT
CMP
CMP
2-/3-/4-PHASE
DRIVER LOGIC
ENSET
RESET
RESET
RESET
RESET
SHUNT
REGULATOR
(ADP3190 ONLY)
18
20
21
22
23
24
25
26
27
131428
EN
11
19
10
15
12
FBRTN
7
VID4
1
VID3
2
VID2
3
VID1
4
VID0
5
VID5
6
FB
8
9
17
16
06529-001
Figure 1.
The ADP3190 is a replacement for the ADP3188. A built-in
shunt regulator allows the part to be connected to the 12 V
system supply through a series resistor.
The device is specified over the commercial temperature
range of 0°C to 85°C and is available in a 28-lead TSSOP and
a 28-lead QSOP.
1
Protected by U. S. Patent Number 6,683,441; other patents pending.
ADP3190
Rev. 2 | Page 2 of 27 | www.onsemi.com
TABLE OF CONTENTS
Features...............................................................................................1
Applications .......................................................................................1
General Description..........................................................................1
Functional Block Diagram...............................................................1
Revision History................................................................................2
Specifications .....................................................................................3
Absolute Maximum Ratings ............................................................5
ESD Caution ..................................................................................5
Pin Configuration and Function Descriptions .............................6
Typical Performance Characteristics and Test Circuits ...............7
Theory of Operation.........................................................................8
Startup Sequence...........................................................................8
Master Clock Frequency ..............................................................8
Output Voltage Differential Sensing ..........................................8
Output Current Sensing...............................................................8
Active Impedance Control Mode ...............................................9
Current-Control Mode and Thermal Balance ..........................9
Voltage Control Mode ..................................................................9
Soft Start.........................................................................................9
Current-Limit, Short-Circuit, and Latch-Off Protection ......10
Dynamic VID ..............................................................................10
Power-Good Monitoring ...........................................................12
Output Crowbar..........................................................................12
Output Enable and UVLO.........................................................12
Application Information ................................................................14
Setting the Clock Frequency .....................................................14
Soft Start and Current-Limit Latch-Off Delay Times............14
Inductor Selection.......................................................................14
Designing an Inductor ...............................................................15
Output Droop Resistance ..........................................................15
Inductor DCR Temperature Correction..................................16
Output Offset...............................................................................16
C
OUT
Selection..............................................................................17
Power MOSFETs .........................................................................17
Ramp Resistor Selection ............................................................19
COMP Pin Ramp........................................................................19
Current-Limit Setpoint ..............................................................19
Feedback Loop Compensation Design ....................................19
C
IN
Selection and Input Current dI/dt Reduction..................21
Tuning the ADP3190..................................................................21
Replacing the ADP3188 with the ADP3190 ...........................23
Choosing Between the ADP3190 and the ADP3190A..........24
Layout and Component Placement..............................................25
General Recommendations.......................................................25
Power Circuitry Recommendations .........................................25
Signal Circuitry Recommendations .........................................25
Outline Dimensions........................................................................26
Ordering Guide ...........................................................................26
REVISION HISTORY
01/08 - Rev 2: Conversion to ON Semiconductor
2/07—Rev. 0 to Rev. A
Changes to Figure 5 ..........................................................................7
Changes to Figure 9 ........................................................................13
Changes to Figure 17 ......................................................................24
Changes to Figure 18 ......................................................................25
1/06—Revision 0: Initial Version
ADP3190
Rev. 2 | Page 3 of 27 | www.onsemi.com
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, T
A
= 0°C to 85°C, unless otherwise noted.
1
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
ERROR AMPLIFIER
Output Voltage Range V
COMP
0 VCC V
Accuracy V
FB
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP, V
OUT
< 1 V
−8.0 +8.0 mV
Relative to nominal DAC output, referenced
to FBRTN, CSSUM = CSCOMP, V
OUT
> 1 V
−9.5 +9.5 mV
Line Regulation
ΔV
FB
VCC = 4.75 V to 5.25 V 0.05 %
Input Bias Current I
FB
14 15.5 17 μA
FBRTN Current I
FBRTN
100 140 μA
Output Current I
O(ERR)
FB forced to V
OUT
– 3% 500 μA
Gain Bandwidth Product GBW
(ERR)
COMP = FB 20 MHz
Slew Rate C
COMP
= 10 pF 25 V/μs
VID INPUTS
Input Low Voltage V
IL(VID)
0.4 V
Input High Voltage V
IH(VID)
0.8 V
Input Current, Input Voltage Low I
IL(VID)
VID(X) = 0 V −25 −35 μA
Input Current, Input Voltage High I
IH(VID)
VID(X) = 1.25 V 5 15 μA
Pull-Up Resistance R
VID
35 60 85 kΩ
Internal Pull-Up Voltage 1.0 1.2 V
VID Transition Delay Time
2
VID code change to FB change 400 ns
No CPU Detection Turn-off Delay
Time
2
VID code change to 11111 to PWM going low 400 ns
OSCILLATOR
Frequency Range
2
f
OSC
0.25 4 MHz
Frequency Variation f
PHASE
T
A
= 25°C, R
T
= 225 kΩ, 4-phase 155 200 245 kHz
T
A
= 25°C, R
T
= 100 kΩ, 4-phase 400 kHz
T
A
= 25°C, R
T
= 30 kΩ, 4-phase 600 kHz
Output Voltage V
RT
R
T
= 100 kΩ to GND 1.8 2.0 2.3 V
RAMPADJ Output Voltage V
RAMPADJ
RAMPADJ − FB −50 +50 mV
RAMPADJ Input Current Range I
RAMPADJ
0 100 μA
CURRENT SENSE AMPLIFIER
Offset Voltage V
OS(CSA)
CSSUM − CSREF −1.5 +1.5 mV
Input Bias Current I
BIAS(CSSUM)
−10 +10 nA
Gain Bandwidth Product GBW
(CSA)
10 MHz
Slew Rate C
CSCOMP
= 10 pF 10 V/μs
Input Common-Mode Range CSSUM and CSREF 0 3 V
Positioning Accuracy
ΔV
FB
See Figure 5 −77 −80 –83 mV
Output Voltage Range 0.05 VCC V
Output Current I
CSCOMP
500 μA
CURRENT BALANCE CIRCUIT
Common-Mode Range V
SWxCM
−600 +200 mV
Input Resistance R
SWx
SWx = 0 V 12 20 28 kΩ
Input Current I
SWx
SWx = 0 V 5 11 17 μA
Input Current Matching
3
ΔI
SWx
SWx = 0 V −5 +5 %
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ADP3190AJRUZ-RL

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Buy ADP3190AJRUZ-RL
Manufacturer:
ON Semiconductor
Description:
Switching Controllers CMOS VER ADP3188
Lifecycle:
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