ADP3190
Rev. 2 | Page 14 of 27 | www.onsemi.com
APPLICATION INFORMATION
The design parameters for a typical Intel VRD 10.1-compliant
CPU application are as follows:
• Input voltage (V
IN
) = 12 V
• VID setting voltage (V
VID
) = 1.300 V
• Duty cycle (D) = 0.108
• Nominal output voltage at no load (V
ONL
) = 1.281 V
• Nominal output voltage at 101 A load (V
OFL
) = 1.180 V
• Static output voltage drop based on a 1.0 mΩ load line (R
O
)
from no load to full load (V
D
) = V
ONL
− V
OFL
=
1.281 V − 1.180 V = 101 mV
• Maximum output current (I
O
) = 119 A
• Maximum output current step (∆I
O
) = 95 A
• Number of phases (n) = 4
• Switching frequency per phase (f
SW
) = 330 kHz
SETTING THE CLOCK FREQUENCY
The ADP3190 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (R
T
). The clock
frequency and the number of phases determine the switching
frequency per phase, which directly relates to switching losses
and the sizes of the inductors and/or the input and output
capacitors. With n = 4 for four phases, a clock frequency of
1.32 MHz sets the switching frequency (f
SW
) of each phase to
330 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Figure 3 shows that to achieve 1.32 MHz oscillator frequency,
the correct value for R
T
is 130 kΩ. Alternatively, the value for R
T
can be calculated using
k31
pF7.4
1
−
××
=
SW
T
fn
R
(1)
where 4.7 pF and 31 kΩ are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended.
SOFT START AND CURRENT-LIMIT LATCH-OFF
DELAY TIMES
Because the soft start and current-limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set C
DLY
for the soft start ramp. This
ramp is generated with a 20 µA internal current source. The
value of R
DLY
has a second-order impact on the soft start time
because it sinks part of the current source to ground.
However, as long as R
DLY
is kept greater than 200 kΩ, this effect
is minor. The value for C
DLY
can be approximated using
VID
SS
DLY
VID
DLY
V
t
R
V
C ×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×
−=
2
A20 (2)
where
t
SS
is the desired soft start time.
Assuming an R
DLY
of 390 kΩ and a desired soft start time of 3
ms, C
DLY
is 36 nF. The closest standard value for C
DLY
is 39 nF.
Once C
DLY
is chosen, R
DLY
can be calculated for the current-limit
latch-off time using
DLY
DELAY
DLY
C
R
×
=
96.1
(3)
If the result for R
DLY
is less than 200 kΩ, a smaller soft start time
should be considered by recalculating the equation for C
DLY
, or
a longer latch-off time should be used. R
DLY
should never be less
than 200 kΩ. In this example, a delay time of 9 ms results in
R
DLY
= 452 kΩ. The closest standard 5% value is 470 kΩ.
INDUCTOR SELECTION
The choice of inductance for the inductor determines the ripple
current in the inductor. Less inductance leads to more ripple
current, which increases the output ripple voltage and conduction
losses in the MOSFETs, but it allows using smaller inductors
and, for a specified peak-to-peak transient deviation, less total
output capacitance.
Conversely, a higher inductance means lower ripple current and
reduced conduction losses but requires larger inductors and
more output capacitance for the same peak-to-peak transient
deviation. In any multiphase converter, a practical value for the
peak-to-peak inductor ripple current is less than 50% of the
maximum dc current in the same inductor. Equation 4 shows the
relationship between the inductance, oscillator frequency, and
peak-to-peak ripple current in the inductor.
()
Lf
DV
I
SW
VID
R
×
−×
=
1
(4)
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
RIPPLE
SW
OVID
Vf
DnRV
L
×
×−××
≥
1
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
()
nH224
mV10kHz330
0.4321m1.0V1.3
=
×
−××
≥L
If the resulting ripple voltage is less than it is designed
for, make the inductor smaller until the ripple value is met.
