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ADP3190AJRUZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
ADP3190
Rev. 2 | Page 4 of 27 | www.onsemi.com
Parameter Symbol Conditions Min Typ Max Unit
CURRENT-LIMIT COMPARATOR
Output Voltage
Normal Mode V
ILIMIT(NM)
EN > 0.8 V, R
ILIMIT
= 250 kΩ 2.8 3 3.3 V
In Shutdown V
ILIMIT(SD)
EN < 0.4 V, I
ILIMIT
= –100 μA 400 mV
Output Current, Normal Mode I
ILIMIT(NM)
EN > 0.8 V, R
ILIMIT
= 250 kΩ 12 μA
Maximum Output Current
2
60 μA
Current-Limit Threshold Voltage V
CL
V
CSREF
– V
CSCOMP
, R
ILIMIT
= 250 kΩ 105 125 145 mV
Current-Limit Setting Ratio V
CL
/I
ILIMIT
10.4 mV/μA
DELAY Normal Mode Voltage V
DELAY(NM)
R
DELAY
= 250 kΩ 2.8 3 3.3 V
DELAY Overcurrent Threshold V
DELAY(OC)
R
DELAY
= 250 kΩ 1.6 1.9 2.2 V
Latch-Off Delay Time t
DELAY
R
DELAY
= 250 kΩ, C
DELAY
= 12 nF 1.5 ms
SOFT START
Output Current, Soft Start Mode I
DELAY(SS)
During startup, DELAY < 2.8 V, 15 20 25 μA
Soft Start Delay Time t
DELAY(SS)
R
DELAY
= 250 kΩ, C
DELAY
= 12 nF,
VID code = 011111
1 ms
ENABLE INPUT
Input Low Voltage V
IL(EN)
0.4 V
Input High Voltage V
IH(EN)
0.8 V
Input Current I
IL(EN)
−1 +1 μA
POWER-GOOD COMPARATOR
Undervoltage Threshold V
PWRGD(UV)
Relative to nominal DAC output −180 −250 −300 mV
Overvoltage Threshold V
PWRGD(OV)
Relative to nominal DAC output 90 150 200 mV
Output Low Voltage V
OL(PWRGD)
I
PWRGD(SINK)
= 4 mA 225 400 mV
Power-Good Delay Time
During Soft Start R
DELAY
= 250 kΩ, C
DELAY
= 12 nF,
VID code = 011111
1 ms
VID Code Changing 100 250 μs
VID Code Static 200 ns
Crowbar Trip Point V
CROWBAR
Relative to nominal DAC output 90 150 200 mV
Crowbar Reset Point Relative to FBRTN 450 550 650 mV
Crowbar Delay Time t
CROWBAR
Overvoltage to PWM going low
VID Code Changing Blanking time 100 250 μs
VID Code Static 400 ns
PWM OUTPUTS
Output Low Voltage V
OL(PWM)
I
PWM(SINK)
= –400 μA 160 500 mV
Output High Voltage V
OH(PWM)
I
PWM(SOURCE)
= +400 μA 4.0 5 V
SUPPLY—ADP3190
4
V
SYSTEM
= 12 V, R
SHUNT
= 240 Ω, see Figure 4
VCC VCC 5 V
DC Supply Current 20 30 mA
UVLO Threshold Voltage V
UVLO
VCC rising 6.3 7 8.0 V
UVLO Hysteresis 0.9 V
SUPPLY—ADP3190A
4
V
SYSTEM
= 5 V, R
SHUNT
= 10 Ω, see Figure 4
VCC VCC 5 V
DC Supply Current 7 12 mA
UVLO Threshold Voltage V
UVLO
VCC rising 3.7 4.0 4.3 V
UVLO Hysteresis 0.9 V
1
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2
Guaranteed by design, not production tested. Specifications subject to change without notice.
3
Relative current matching from each phase to the average of all four phases.
4
System supply is the only difference between the ADP3190 and ADP3190A. All other parameters are the same for the two models.
ADP3190
Rev. 2 | Page 5 of 27 | www.onsemi.com
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC −0.3 V to +6 V
VID Pins −0.3 V to +6 V
FBRTN −0.3 V to +0.3 V
SW1 to SW4 −5 V to +25 V
All Other Inputs and Outputs −0.3 V to VCC + 0.3 V
Storage Temperature Range −65°C to +150°C
Operating Ambient Temperature Range 0°C to 85°C
Operating Junction Temperature 125°C
Thermal Impedance (θ
JA
) 100°C/W
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
are referenced to GND.
ESD CAUTION
ADP3190
Rev. 2 | Page 6 of 27 | www.onsemi.com
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADP3190
TOP VIEW
(Not to Scale)
VID3
VID2
VID1
FBRTN
VID5
VID0
VID4
PWM1
PWM2
PWM3
SW2
SW1
PWM4
FB
COMP
PWRGD
RAMPADJ
DELAY
EN
SW3
SW4
GND
ILIMIT
RT CSREF
CSSUM
CSCOMP
VCC
06529-005
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 6 VID4 to VID0,
VID5
Voltage Identification DAC Inputs. These six pins are pulled up to an internal reference, providing a Logic 1
if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8375 V to
1.6 V (see Table 4). Leaving all the VID pins open results in ADP3190 going into a “No CPU” mode, shutting off their
PWM outputs and pulling the PWRGD output low.
7 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
8 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin
and the output voltage sets the no-load offset point.
9 COMP Error Amplifier Output and Compensation Point.
10 PWRGD Power Good Output. Open drain output that signals when the output voltage is outside of the proper operating
range.
11 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
12 DELAY Soft Start Delay and Current-Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time.
13 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
14 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM
ramp.
15 ILIMIT Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the
converter. This pin is actively pulled low when the ADP3190 EN input is low or when VCC is below its UVLO
threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
16 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the
output inductors.
17 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
18 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of the load
line and the positioning loop response time.
19 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
20 to 23 SW4 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should
be left open.
24 to 27 PWM4 to PMW1 Logic Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the
ADP3120A. Connecting the PWM3 and/or PWM4 outputs to GND causes that phase to turn off, allowing the
ADP3190 to operate as a 2-, 3-, or 4-phase controller.
28 VCC ADP3190: A 240 Ω resistor should be placed between the 12 V system supply and the VCC pin to ensure 5 V.
ADP3190A: A 10 Ω resistor should be placed between the 5 V system supply and the VCC pin to ensure 5 V.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ADP3190AJRUZ-RL

Mfr. #:
Buy ADP3190AJRUZ-RL
Manufacturer:
ON Semiconductor
Description:
Switching Controllers CMOS VER ADP3188
Lifecycle:
New from this manufacturer.
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