LTC4258CGW#TRPBF Datasheet LTC4258CGW#PBF, LTC4258CGW#TRPBF | P10-P12

LTC4258

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Interrupt Registers

Interrupt (Address 00h): Interrupt Register, Read Only. A

transition to logical 1 of any bit in this register will assert

the INT pin (Pin 3) if the corresponding bit in the Int Mask

ing bits in the Event registers. The Interrupt register is Read

Only and its bits cannot be cleared directly. To clear a bit

in the Interrupt register, clear the corresponding bits in the

appropriate Status or Event registers or set bit 7 in the Reset

Pushbutton register (1Ah).

Int Mask (Address 01h): Interrupt Mask, Read/Write. A logic

1 in any bit of the Int Mask register allows the correspond-

ing Interrupt register bit to assert the INT pin if it is set. A

logic 0 in any bit of the Int Mask register prevents the cor-

responding Interrupt bit from affecting the INT pin. The

actual Interrupt register bits are unaffected by the state of

the Int Mask register.

Event Registers

Power Event (Address 02h): Power Event Register, Read

Only. The lower four bits in this register indicate that the

corresponding port Power Enable status bit has changed;

the logical OR of these four bits appears in the Interrupt

indicate that the corresponding port Power Good status bit

has changed; the logical OR of these four bits appears in

the Interrupt register as the Pwr Good Event bit. The Power

Event bits latch high and will remain high until cleared by

reading from address 03h.

Power Event CoR (Address 03h): Power Event Register,

Clear on Read. Read this address to clear the Power Event

and reading address 03h clears all bits at both addresses.

Detect Event (Address 04h): Detect Event Register, Read

Only. The lower four bits in this register indicate that at least

one detection cycle for the corresponding port has com-

pleted; the logical OR of these four bits appears in the In-

terrupt register as the Detect Complete bit. The upper four

bits indicate that at least one classification cycle for the

corresponding port has completed; the logical OR of these

four bits appears in the Interrupt register as the Class Com-

plete bit. In Manual mode, this register indicates that the

requested detection/classification cycle has completed and

the LTC4258 is awaiting further instructions. In Semiauto

or Auto modes, these bits indicate that the Detect Status

and Class Status bits in the Port Status registers are valid.

The Detect Event bits latch high and will remain high until

cleared by reading from address 05h.

Detect Event CoR (Address 05h): Detect Event Register,

Clear on Read. Read this address to clear the Detect Event

and reading address 05h clears all bits at both addresses.

Fault Event (Address 06h): Fault Event Register, Read Only.

The lower four bits in this register indicate that a

ICUT

fault has occurred at the corresponding port; the logi-

cal OR of these four bits appears in the Interrupt register

as the t

ICUT

Fault bit. The upper four bits indicate that a Dis-

connect event has occurred at the corresponding port; the

logical OR of these four bits appears in the Interrupt reg-

ister as the Disconnect bit. The Fault Event bits latch high

and will remain high until cleared by reading from address

07h.

Fault Event CoR (Address 07h): Fault Event Register, Clear

on Read. Read this address to clear the Fault Event regis-

ter. Address 07h returns the same data as address 06h and

reading address 07h clears all bits at both addresses.

START

Event (Address 08h): t

START

Event Register, Read

Only. The lower four bits in this register indicate that a t

START

fault has occurred at the corresponding port; the logical OR

of these four bits appears in the Interrupt register as the

START

Fault bit. The t

START

Event bits latch high and will

remain high until cleared by reading from address 09h. The

upper four bits in this register are reserved and will always

read as 0.

START

Event CoR (Address 09h): t

START

Event Register,

Clear on Read. Read this address to clear the Fault Event

and reading address 09h clears all bits at both addresses.

Supply Event (Address 0Ah): Supply Event Register, Read

Only. Bit 4 indicates that V

has dropped below the V

UVLO level (typically –28V). Bit 5 signals that the V

supply

has dropped below the V

UVLO threshold. Bit 7 indicates

that the LTC4258 die temperature has exceeded its thermal

shutdown limit (see Note 4 under Electrical Characteris-

tics). The logical OR of bits 4, 5 and 7 appears in the Inter-

rupt register as the Supply Fault bit. The remaining bits in

LTC4258

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the register are reserved and will always read as 0. The

Supply Event bits latch high and will remain high until

cleared by reading from address 0Bh.

Supply Event CoR (Address 0Bh): Supply Event Register,

Clear on Read. Read this address to clear the Fault Event

and reading address 0Bh clears all bits at both addresses.

Status Registers

Port 1 Status (Address 0Ch): Port 1 Status Register, Read

Only. This register reports the most recent detection and

classification results for port 1. Bits 0-2 report the status

of the most recent detection attempt at the port and bits 4-6

report the status of the most recent classification attempt

at the port. If power is on, these bits report the detection/

classification status present just before power was turned

on. If power is turned off at the port for any reason, all bits

in this register will be cleared. See Table 1 for detection and

classification status bit encoding.

Port 2 Status (Address 0Dh): Port 2 Status Register, Read

Only. See Port 1 Status.

Port 3 Status (Address 0Eh): Port 3 Status Register, Read

Only. See Port 1 Status.

Port 4 Status (Address 0Fh): Port 4 Status Register, Read

Only. See Port 1 Status.

Power Status (Address 10h): Power Status Register, Read

Only. The lower four bits in this register report the switch

on/off state for the corresponding ports. The upper four

bits (the power good bits) indicate that the drop across the

power switch and sense resistor for the corresponding ports

is less than 2V (typ) and power start-up is complete. The

power good bits are latched high and are only cleared when

a port is turned off or the LTC4258 is reset.

Pin Status (Address 11h): External Pin Status, Read Only.

This register reports the real time status of the AUTO

(Pin 35) and AD0-AD3 (Pins 7-10) digital input pins. The

logic state of the AUTO pin appears at bit 0 and the AD0-AD3

pins at bits 2-5. The remaining bits are reserved and will

read as 0. AUTO affects the initial states of some of the

LTC4258 configuration registers at start-up but has no

effect after start-up and can be used as a general purpose

input if desired, as long as it is guaranteed to be in the

appropriate state at start-up.

Configuration Registers

Operating Mode (Address 12h): Operating Mode Configu-

ration, Read/Write. This register contains the mode bits for

each of the four ports in the LTC4258. See Table 1 for mode

bit encoding. At power-up, all bits in this register will be set

to the logic state of the AUTO pin (Pin 35). See Operating

Modes in the Applications Information section.

Disconnect Enable (Address 13h): Disconnect Enable

enable or disable DC disconnect detection circuitry at the

corresponding port. If the DC Discon Enable bit is set the

port circuitry will turn off power if the current draw at the

port falls below I

MIN

for more than t

DIS

. I

MIN

is equal to V

MIN

, where R

is the sense resistor and should be 0.5Ω for

IEEE 802.3af compliance. If the bit is clear the port will not

remove power due to low current.

Detect/Class Enable (Address 14h): Detection and Clas-

sification Enable, Read/Write. The lower four bits of this reg-

ister enable the detection circuitry at the corresponding port

if that port is in Auto or Semiauto mode. The upper four bits

enable the classification circuitry at the corresponding port

if that port is in Auto or Semiauto mode. In manual mode,

setting a bit in this register will cause the LTC4258 to per-

form one classification or detection cycle on the corre-

sponding port. Writing to the Detect/Class Restart PB (18h)

has the same effect without disturbing the Detect/Class

Enable bits for other ports.

Timing Config (Address 16h): Global Timing Configuration,

Read/Write. Bits 0-1 program t

DIS

, the time duration before

a port is automatically tuned off after the PD is removed.

Bits 2-3 program t

ICUT

, the time during which a port’s

current can exceed I

CUT

without it being turned off. If the

current is still above I

CUT

after t

ICUT

, the LTC4258 will in-

dicate a t

ICUT

fault and turn the port off. Bits 4-5 program

START

, the time duration before an overcurrent condition

during port power-on is considered a t

START

fault and the

port is turned off. Note that using the t

ICUT

and t

START

times

other than the default is not compliant with IEEE 802.3af

and may double or quadruple the energy dissipated by the

external MOSFETs during fault conditions. Bits 6-7 are re-

served and should be read/written as 0. See Electrical Char-

acteristics for timer bit encoding. Also see the Applications

Information for descriptions of t

START

, t

ICUT

and DC discon-

nect timing.

LTC4258

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shutdown, regardless of the state of detection or classifi-

cation. Note that t

ICUT

, t

START

and disconnect events (if

enabled) will still turn off power if they occur.

The Power Enable bit cannot be set if the port has turned

off due to a t

ICUT

or t

START

fault and the t

ICUT

timer has not

yet counted back to zero. See Applications Information for

more information on t

ICUT

timing.

Clearing the Power Enable bits with this register also

clears the detect and fault event bits, the Port Status

for the affected port(s).

Reset PB (Address 1Ah): Reset Pushbutton, Write Only.

Bits 0-3 reset the corresponding port by clearing the power

enable bit, the detect and fault event bits, the status regis-

ter and the detection and classification enable bits for that

port. Bit 4 returns the entire LTC4258 to the power-on

reset state; all ports are turned off, the AUTO pin is reread

and all registers are returned to their power-on defaults,

except V

UVLO, which remains cleared. Bit 5 is reserved;

setting it has no effect. Setting bit 6 releases the Interrupt

pin if it is asserted without affecting the Event registers or

the Interrupt register. When the INT pin is released in this

way, the condition causing the LTC4258 to pull the INT pin

down must be removed before the LTC4258 will be able to

pull INT down again. This can be done by reading and

clearing the event registers or by writing a 1 into bit 7 of

this register. Setting bit 7 releases the Interrupt pin, clears

all the Event registers and clears all the bits in the Interrupt

Misc Config (Address 17h): Miscellaneous Configuration,

Read/Write. Setting bit 7 enables the INT pin. If this bit is

reset, the LTC4258 will not pull down the INT pin in any

condition nor will it respond to the Alert Response Address.

This bit is set by default.

Pushbutton Registers

Note Regarding Pushbutton Registers: “Pushbutton” reg-

isters are specialized registers that trigger an event when

a 1 is written to a bit; writing a 0 to a bit will do nothing. Unlike

a standard read/write register, where setting a single bit

involves reading the register to determine its status, set-

ting the appropriate bit in software and writing back the

entire register, a pushbutton register allows a single bit to

be written without knowing or affecting the status of the

other bits in the register. Pushbutton registers are write-

only and will return 00h if read.

Det/Class Restart PB (Address 18h): Detection/Classifi-

cation Restart Pushbutton Register, Write Only. Writing a

1 to any bit in this register will start or restart a single

detection or classification cycle at the corresponding port

in Manual mode. It can also be used to set the correspond-

ing bits in the Detect/Class Enable register (address 14h)

for ports in auto or semiauto mode. The lower 4 bits affect

detection on each port while the upper 4 bits affect

classification.

Power Enable PB (Address 19h): Power Enable Pushbutton

the Power Enable bit in the corresponding Port Status reg-

ister; the upper four bits clear the corresponding Power

Enable bit. Setting or clearing the Power Enable bits via this

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LTC4258CGW#TRPBF

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Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN 4x IEEE 802.3af Pwr over E Cntr w/ Int D

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LTC4258CGW#TRPBF

LTC4258CGW#TRPBF

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