LTC4258
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Choosing External MOSFETs
Power delivery to the ports is regulated with external
power MOSFETs. These MOSFETs are controlled as previ-
ously described to meet the IEEE 802.3af specification.
Under normal operation, once the port is powered and the
PD’s bypass capacitor is charged to the port voltage, the
external MOSFET dissipates very little power. This sug-
gests that a small MOSFET is adequate for the job. Unfor-
tunately, other requirements of the IEEE 802.3af mandate
a MOSFET capable of dissipating significant power. When
the port is being powered up, the port voltage must reach
30V or more before the PD turns on. The port voltage can
then drop to 0V as the PD’s bypass capacitor is charged.
According to the IEEE, the PD can directly connect a 180µF
capacitor to the port and the PSE must charge that
capacitor with a current limit of 400mA to 450mA for at
least 50ms.
An even more extreme example is a noncompliant PD that
provides the proper signature during detection but then
behaves like a low valued resistor, say 50, in parallel with
a 1µF capacitor. When the PSE has charged this
noncompliant PD up to 20V, the 50 resistor will draw
400mA (the minimum IEEE prescribed I
LIM
current limit)
keeping the port voltage at 20V for the remainder of t
START
.
The external MOSFET sees 24V to 37V V
DS
at 400mA to
450mA, dissipating 9.6W to 16.7W for 60ms (typ).
The LTC4258 implements foldback to reduce the current
limit when the MOSFET V
DS
is high; see the Foldback
section. Without foldback, the MOSFET could see as much
as 25.7W for 60ms (typ) when powering a shorted or a
noncompliant PD with only a few ohms of resistance. With
foldback, the MOSFET sees a maximum of 18W for the
duration of t
START
.
The LTC4258’s duty cycle protection enforces 15 times
longer off time than on time, preventing successive at-
tempts to power a defective PD from damaging the MOS-
FET. System software can enforce even longer wait times.
When the LTC4258 is operated in semiauto or manual
mode—described in more detail under Operating Modes—
it will not power on a port until commanded to do so by the
host controller. By keeping track of t
START
and t
ICUT
faults,
the host controller can delay turning on the port again after
one of these faults even if the LTC4258 reports a Detect
Good. In this way the host controller implements a MOS-
FET cooling off period which may be programmed to
protect smaller MOSFETs from repeated thermal cycling.
The LTC4258 has built-in duty cycle protection for t
ICUT
and t
START
(see t
ICUT
Timing and t
START
Timing sections)
that is sufficient to protect the MOSFETs shown in
Figure 1.
Before designing a MOSFET into your system, carefully
compare its safe operating area (SOA) with the worst case
conditions (like powering up a defective PD) the device will
face. Using transient suppressors, polyfuses and ex-
tended wait times after disconnecting a PD are effective
strategies to reduce the extremes applied to the external
MOSFETs.
Surge Suppressors and Circuit Protection
IEEE 802.3af Power over Ethernet is a challenging Hot Swap
application because it must survive the (probably unin-
tentional) abuse of everyone in the building. While hot
swapping boards in a networking or telecom card cage is
done by a trained technician or network administrator,
anyone in the building can plug a device into the network.
Moreover, in a card cage the physical domain being pow-
ered is confined to the card cage. With Power over Ether-
net, the PSE supplies power to devices up to 100 meters
away. Ethernet cables could potentially be cut, shorted
together, and so on by all kinds of events from a contrac-
tor cutting into walls to someone carelessly sticking a
screwdriver where it doesn’t belong. Consequently, the
Power over Ethernet power source (PSE) must be designed
to handle these events.
The most dramatic of these is shorting a powered port.
What the PSE sees depends on how much CAT-5 cable is
between it and the short. If the short occurs on the far end
of a long cable, the cable inductance will prevent the
APPLICATIO S I FOR ATIO
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LTC4258
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APPLICATIO S I FOR ATIO
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current in the cable from increasing too quickly and the
LTC4258’s built-in short-circuit protection will take con-
trol of the situation and turn off the port. Some energy is
stored in the cable, but the transient suppressor on the
port clamps the port voltage when the cable inductance
causes the voltage to fly back after the MOSFET is turned
off. Because the cable only had 600mA or so going through
it, an SMAJ58A or equivalent device can easily control the
port voltage during flyback. With no cable connected at all,
a powered port shorted at the PSE’s RJ-45 connector can
reach high current levels before the port is shut down. There
is no cable inductance to store energy so once the port is
shut down the situation is under control.
A short—hence low inductance—piece of CAT-5 will not
limit the rapid increase of current when the port is shorted.
Even though the LTC4258 short-circuit shutdown is fast,
the cable may have many amps flowing through it before
the MOSFET can be turned off. Due to the high current,
this short piece of cable flies back with significant energy
behind it and must be controlled by the transient suppres-
sor. Choosing a surge suppressor that will not develop
more than a few volts of forward voltage while passing
more than 10A is important. A positive port voltage may
forward bias the detect diode (D
DET
n
), bringing the
LTC4258’s DETECT
n
pin positive as well and engaging
the DETECT
n
clamps. This will generally not damage the
LTC4258 but extreme cases can cause the LTC4258 to
reset. When it resets, the LTC4258 signals an interrupt,
alerting the host con
troller which can then return the
LTC4258 to normal operating mode.
A substantial transient surge suppressor can typically
protect the LTC4258 and the rest of the PSE from these
faults. Placing a polyfuse between the RJ-45 connector
and the LTC4258 and its associated circuitry can provide
additional protection. To meet safety requirements, place
the polyfuse in the ground leg of the PSE’s output.
DC DISCONNECT
DC disconnect monitors the sense resistor voltage when-
ever the power is on to make sure that the PD is drawing
the minimum specified current. The disconnect timer
counts up whenever port current is below 7.5mA (typ). If
the t
DIS
timer runs out, the corresponding port will be
turned off and the disconnect bit in the fault register will be
set. If the undercurrent condition goes away before the
t
DIS
timer runs out, the timer will reset. The timer will start
counting from the beginning if the under
current condition
occurs again. The undercurrent circuit includes a glitch
filter to filter out noise.
The DC disconnect feature can be disabled by clearing the
corresponding DC Discon Enable bits in the Disconnect
register (13h). The t
DIS
timer duration can be programmed
by bits 1 and 0 of register 16h.
The LTC4258 implements a variety of current sense and
limit thresholds to control current flowing through the
port. Figure 16 is a graphical representation of these
thresholds and the action the LTC4258 takes when
currrent crosses the thresholds.
Figure 16. LTC4258 Current Sense and Limits
0mA0mV
100mA
CURRENT
R
S
= 0.5
DC DIS-
CONNECT
CUT
(I
CUT
)
LIMIT
(I
LIM
)
SHORT
CIRCUIT
EFFECTSENSE
n
VOLTAGE
50mV
200mA100mV
300mA150mV
400mA200mV
500mA250mV
600mA300mV
CURRENT
LIMIT
PORT OFF IN t
ICUT
OR t
START
CURRENT LIMIT
IN 1µs
NORMAL
OPERATION
PORT OFF IN t
DIS
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LTC4258
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SERIAL DIGITAL INTERFACE
The LTC4258 communicates with a host (master) using
the standard 2-wire interface as described in the SMBus
Specification Version 2.0 (available at http://smbus.org).
The SMBus is an extension of the I
2
C bus, and the
LTC4258 is also compatible with the I
2
C bus standard. The
Timing Diagrams (Figures 5 through 9) show the timing
relationship of the signals on the bus. The two bus lines,
SDA and SCL, must be high when the bus is not in use.
External pull-up resistors or current sources, such as the
LTC1694 SMBus accelerator, are required on these lines.
If the SDA and SCL pull-ups are absent, not connected to
the same positive supply as the LTC4258’s V
DD
pin, or are
not activated when the power is applied to the LTC4258, it
is possible for the LTC4258 to see a START condition on
the I
2
C bus. The interrupt pin (INT) is only updated
between I
2
C transactions. Therefore if the LTC4258 sees
a START condition when it powers up because the SCL and
SDA lines were left floating, it will not assert an interrupt
(pull INT low) until it sees a STOP condition on the bus. In
a typical application the I
2
C bus will immediately have
traffic and the LTC4258 will see a STOP so soon after
power up that this momentary condition will go unnoticed.
Isolating the Serial Digital Interface
IEEE 802.3af requires that network segments be electri-
cally isolated from the chassis ground of each network
interface device. However, the network segments are not
required to be isolated from each other provided that the
segments are connected to devices residing within a
single building on a single power distribution system.
For simple devices such as small powered Ethernet
switches, the requirement can be met by using an iso-
lated power supply to power the entire device. This
implementation can only be used if the device has no
electrically conducting ports other than twisted-pair
Ethernet. In this case, the SDAIN and SDAOUT pins of the
LTC4258 can be connected together to act as a standard
I
2
C/SMBus SDA pin.
If the device is part of a larger system, contains serial
ports, or must be referenced to protective ground for
some other reason, the Power over Ethernet subsystem
including the LTC4258s must be electrically isolated
from the rest of the system. The LTC4258 includes
separate pins (SDAIN and SDAOUT) for the input and
output functions of the bidirectional data line. This eases
the use of optocouplers to isolate the data path between
the LTC4258s and the system controller. Figure 17
shows one possible implementation of an isolated inter-
face. The SDAOUT pin of the LTC4258 is designed to
drive the inputs of an optocoupler directly, but a standard
I
2
C device typically cannot. U1 is used to buffer I
2
C
signals into the optocouplers from the system controller
side. Schmitt triggers must be used to prevent extra
edges on transitions of SDA and SCL.
Bus Addresses and Protocols
The LTC4258 is a read-write slave device. The master can
communicate with the LTC4258 using the Write Byte,
Read Byte and Receive Byte protocols. The LTC4258’s
primary serial bus address is (010A
3
A
2
A
1
A
0
)b, as desig-
nated by pins AD3-AD0. All LTC4258s also respond to the
address (0110000)b, allowing the host to write the same
command into all of the LTC4258s on a bus in a single
transaction. If the LTC4258 is asserting (pulling low) the
INT pin, it will also acknowledge the Alert Response
Address (0001100)b using the receive byte protocol.
The START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master (typically the host controller) signals the
beginning of communication with a slave device (like the
LTC4258) by transmitting a START condition. A START
condition is generated by transitioning SDA from high to
low while SCL is high. A REPEATED START condition is
functionally the same as a START condition, but used to
extend the protocol for a change in data transmission
direction. A STOP condition is not used to set up a
REPEATED START condition, for this would clear any data
already latched in. When the master has finished commu-
nicating with the slave, it issues a STOP condition. A STOP
condition is generated by transitioning SDA from low to
high while SCL is high. The bus is then free for communi-
cation with another SMBus or I
2
C device.

LTC4258CGW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN 4x IEEE 802.3af Pwr over E Cntr w/ Int D
Lifecycle:
New from this manufacturer.
Delivery:
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