LTC4258
4
4258fb
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. AGND = DGND = 0V, V
DD
= 3.3V, V
EE
= –48V unless otherwise noted
(Note 5).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
START
Maximum Current Limit Duration During t
START1
= 0, t
START0
= 0 (Figure 3) ● 50 60 70 ms
Port Start-Up t
START1
= 0, t
START0
= 1 (Figure 3) ● 25 30 35 ms
t
START1
= 1, t
START0
= 0 (Figure 3) ● 100 120 140 ms
t
START1
= 1, t
START0
= 1 (Figure 3) ● 200 240 280 ms
t
ICUT
Maximum Current Limit Duration After t
ICUT1
= 0, t
ICUT0
= 0 (Figure 3) ● 50 60 70 ms
Port Start-Up t
ICUT1
= 0, t
ICUT0
= 1 (Figure 3) ● 25 30 35 ms
t
ICUT1
= 1, t
ICUT0
= 0 (Figure 3) ● 100 120 140 ms
t
ICUT1
= 1, t
ICUT0
= 1 (Figure 3) ● 200 240 280 ms
DC
CLMAX
Maximum Current Limit Duty Cycle Reg16h = 00h ● 5.8 6.3 6.7 %
t
DIS
Disconnect Delay t
DIS1
= 0, t
DIS0
= 0 (Figure 4) ● 300 360 400 ms
t
DIS1
= 0, t
DIS0
= 1 (Figure 4) ● 75 90 100 ms
t
DIS1
= 1, t
DIS0
= 0 (Figure 4) ● 150 180 200 ms
t
DIS1
= 1, t
DIS0
= 1 (Figure 4) ● 600 720 800 ms
t
VMIN
DC Disconnect Minimum Pulse V
SENSE
n
– V
EE
> 5mV, V
OUT
n
= –48V (Figure 4) ● 0.02 1 ms
Width Sensitivity (Note 9)
I
2
C Timing
f
SCLK
Clock Frequency (Note 9) ● 400 kHz
t
1
Bus Free Time Figure 5 (Notes 9, 10) ● 1.3 µs
t
2
Start Hold Time Figure 5 (Notes 9, 10) ● 600 ns
t
3
SCL Low Time Figure 5 (Notes 9, 10) ● 1.3 µs
t
4
SCL High Time Figure 5 (Notes 9, 10) ● 600 ns
t
5
Data Hold Time Figure 5 (Notes 9, 10) ● 150 ns
t
6
Data Set-Up Time Figure 5 (Notes 9, 10) ● 200 ns
t
7
Start Set-Up Time Figure 5 (Notes 9, 10) ● 600 ns
t
8
Stop Set-Up Time Figure 5 (Notes 9, 10) ● 600 ns
t
r
SCL, SDAIN Rise Time Figure 5 (Notes 9, 10) ● 20 300 ns
t
f
SCL, SDAIN Fall Time Figure 5 (Notes 9, 10) ● 20 150 ns
t
FLTINT
Fault Present to INT Pin Low (Notes 9, 10, 11) ● 20 150 ns
t
STOPINT
Stop Condition to INT Pin Low (Notes 9, 10, 11) ● 60 200 ns
t
ARAINT
ARA to INT Pin High Time (Notes 9, 10) ● 20 300 ns
pins are negative. All voltages are referenced to ground (AGND and DGND)
unless otherwise specified.
Note 6: The LTC4258 is designed to maintain a port voltage of –46.6V to
–57V. The V
EE
supply voltage range accounts for the drop across the
MOSFET and sense resistor.
Note 7: The LTC4258 implements overload current detection per IEEE
802.3af. The minimum overload current (I
CUT
) is dependent on port
voltage; I
CUT_MIN
= 15.4W/V
PORT_MIN
. An IEEE compliant system using the
LTC4258 should maintain port voltage above –46.6V.
Note 8: V
EE
supply current while classifying a short is measured indirectly
by measuring the DETECT
n
pin current while classifying a short.
Note 9: Guaranteed by design, not subject to test.
Note 10: Values measured at V
ILD
and V
IHD
.
Note 11: If fault occurs during an I
2
C transaction, the INT pin will not be
pulled down until a stop condition is present on the I
2
C bus.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: DGND and AGND should be tied together in normal operation.
Note 3: An internal clamp limits the GATE pins to a minimum of 12V above
V
EE
. Driving this pin beyond the clamp may damage the part.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: All currents into device pins are positive; all currents out of device
