LTC4258
24
4258fb
1Ah). The state of the INT pin can only change between I
2
C
transactions, so an interrupt is cleared or new interrupts
are generated after a transaction completes and before
new I
2
C bus communication commences. Periodic polling
of the alert response address can be used instead of the
INT pin if desired. If any device acknowledges the alert
response address, then the INT line, if connected, would
have been low.
System Software Strategy
Control of the LTC4258 hinges on one decision, the
LTC4258’s operating mode. The three choices are de-
scribed under Operating Modes. In Auto mode the LTC4258
can operate autonomously without direction from a host
controller. Because LTC4258s running in Auto mode will
power every valid PD connected to them, the PSE must
have 15.4W/port available. To reduce the power require-
ments of the –48V supply, PSE systems can track power
usage, only turning on ports when sufficient power is
available. The IEEE describes this as a power allocation
algorithm and places two limitations: the PSE shall not
power a PD unless it can supply the guaranteed power for
that PD’s class (see Table 2) and power allocation may not
be based solely on a history of each PD’s power consump-
tion. In order for a PSE to implement power allocation, the
PSE’s processor/controller must control whether ports
are powered—the LTC4258 cannot be allowed to operate
in Auto mode. Semiauto mode fits the bill as the LTC4258
automatically detects and classifies PDs, then makes this
information available to the host controller, which de-
cides to apply power or not. Operating the LTC4258 in
Manual mode also lets the controller decide whether to
power the ports but the controller must also control
detection and classification. If the host controller oper-
ates near the limit of its computing resources, it may not
be able to guide a Manual mode LTC4258 through detect,
classification and port turn-on in less than the IEEE
mandated maximum of 950ms.
In a typical PSE, the LTC4258s will operate in Semiauto
mode as this allows the controller to decide to power a
port without unduly burdening the controller. With an
interrupt mask of F4h, the LTC4258 will signal to the host
after it has successfully detected and classified a PD, at
APPLICATIO S I FOR ATIO
WUUU
which point the host can decide whether enough power is
available and command the LTC4258 to turn that port on.
Similarly, the LTC4258 will generate interrupts when a
port’s power is turned off. By reading the LTC4258’s
interrupt register, the host can determine if a port was
turned off due to overcurrent (t
START
or t
ICUT
faults) or
because the PD was removed (Disconnect event). The
host then updates the amount of available power to reflect
the power no longer consumed by the disconnected PD.
Setting the MSB of the interrupt mask causes the LTC4258
to communicate fault conditions caused by failures within
the PSE, so the host does not need to poll to check that the
LTC4258s are operating properly. This interrupt driven
system architecture provides the controller with the final
say on powering ports at the same time, minimizing the
controller’s computation requirements because inter-
rupts are only generated when a PD is detected or on a
fault condition.
The LTC4258 can also be used to power older powered
Ethernet devices that are not 802.3af compliant and may
be detected with other methods. Although the LTC4258
does not implement these older detection methods auto-
matically, if software or external circuitry can detect the
noncompliant devices, the host controller may command
the LTC4258 to power the port, bypassing IEEE compliant
detection and classification and sending power to the
noncompliant device.
LOGIC LEVEL SUPPLY
In additon to the 48V used to source power to each port,
a logic level supply is required to power the digital portion
of the LTC4258. To simplify design and meet voltage
isolation requirements, the logic level supply can be
generated from the isolated –48V supply. Figure 18
shows an example method using an LTC3803 to control
a –48V to 3.3V current mode supply. This boost con-
verter topology uses the LTC3803 current mode control-
ler and a current mirror which reflects the 3.3V output
voltage to the –48V rail, improving the regulation toler-
ance over the more traditional large resistor voltage
divider. This approach achieves high accuracy with a
transformerless design.
