µ
PD70F3003A, 70F3025A, 70F3003A(A)
32
Data Sheet U13189EJ5V1DS
(9) CSI timing (1/2)
(a) Master mode
(i) CSI0 to CSI2 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCKn cycle <67> tCYSK1 Output 120 ns
SCKn high-level width <68> tWSKH1 Output 0.5 tCYSK1 – 20 ns
SCKn low-level width <69> tWSKL1 Output 0.5 tCYSK1 – 20 ns
SIn setup time (to SCKn↑)
<70> t
SSISK1 30 ns
SIn hold time (from SCKn↑)
<71> t
HSKSI1 0 ns
SOn output delay time (from SCKn↓)
<72> tDSKSO1 18 ns
SOn output hold time (from SCKn↑)
<73> tHSKSO1 0.5 tCYSK1 – 5 ns
Remark n = 0 to 2
(ii) CSI3 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCK3 cycle <67> tCYSK3 Output 500 ns
SCK3 high-level width <68> tWSKH3 Output
0.5 tCYSK3 – 70 ns
SCK3 low-level width <69> tWSKL3 Output
0.5 tCYSK3 – 70 ns
SI3 setup time (to SCK3↑) <70> tSSISK3 100 ns
SI3 hold time (from SCK3↑) <71> tHSKSI3 50 ns
SO3 output delay time (from SCK3↓)
<72> tDSKSO3 RL = 1.5 KΩ 150 ns
CL = 50 pF
SO3 output hold time (from SCK3↑)
<73> tHSKSO3 0.5 tCYSK3 – 5 ns
Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output
lines.
(b) Slave mode
(i) CSI0 to CSI2 timing
Parameter Symbol Conditions MIN. MAX. Unit
SCKn cycle <67> tCYSK2 Input 120 ns
SCKn high-level width <68> tWSKH2 Input 30 ns
SCKn low-level width <69> tWSKL2 Input 30 ns
SIn setup time (to SCKn↑) <70> tSSISK2 10 ns
SIn hold time (from SCKn↑) <71> tHSKSI2 10 ns
SOn output delay time (from SCKn↓)
<72> tDSKSO2 30 ns
SOn output hold time (from SCKn↑)
<73> tHSKSO2 tWSKH2 ns
Remark n = 0 to 2
RL = 1.5
kΩ
CL = 50
pF
