ICS870919BVI REVISION B JANUARY 10, 2012 3 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistor. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1, 13, 17, 20, 24 GND Power
Power supply ground.
2 nQ5 Output
Single-ended clock output (phase is inverted with respect to other outputs).
LVCMOS/LVTTL interface levels
3, 15, 22, 27 V
DD
Power
Positive power supply pins.
4 OE/nRST Input
Output enable and asynchronous reset. Resets all outputs. Logic LOW, the
outputs are in a high impedance state. Logic HIGH enables all outputs.
Internally a Power On reset circuit will ensure that the nQ5 output is inverted
relative to Q[4:0]. If OE/nRST is pulsed low, it must be held low for a minimum of
10 ns for a complete reset operation. This reset may be applied asynchronously
to the input reference.
5 FEEDBACK Input
PLL feedback input which is connected to one of the clock outputs to close the
PLL feedback loop. LVCMOS/LVTTL interface levels.
6 REF_SEL Input
Input reference clock select. Logic LOW selects the SYNC0. Logic HIGH selects
the SYNC1 input as the PLL reference input. LVCMOS/LVTTL interface levels.
7,
11
SYNC0,
SYNC1
Input
Single-ended reference clock inputs. LVCMOS/LVTTL interface levels.
8 AVDD Power
Positive power supply for the PLL.
9 nPE Input Pulldown
Output phase synchronization. In PLL mode (PLL_EN = HIGH) and when logic
LOW, the rising edges of the outputs (2XQ, Q0:Q4, Q/2) are synchronized to the
rising edge of the selected reference clock (SYNCn). In PLL mode (PLL_EN =
HIGH) and when logic HIGH, the falling edges of the outputs (2XQ, Q0:Q4, Q/2)
are synchronized to the falling edge of the selected reference clock (SYNCn).
LVCMOS/LVTTL interface levels.
10 AGND Power
Power supply ground for the PLL. Internally connected to GND.
12 FREQ_SEL Input
Frequency select. Logic LOW level inserts a divide-by-2 into the PLL output and
feedback path. Logic HIGH inserts a divide-by-1 into the PLL output and
feedback path. LVCMOS/LVTTL interface levels.
14, 16,
21, 23, 28
Q0, Q1,
Q2, Q3, Q4
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
18 PLL_EN Input
PLL enable. Enable and disables the PLL. Logic HIGH enables the PLL. Logic
LOW disables the PLL and the input reference signal is routed to the output
dividers (PLL bypass). LVCMOS/LVTTL interface levels.
19 LOCK Output
PLL lock indication output. Logic HIGH indicates PLL lock. Logic LOW indicates
PLL is not locked. LVCMOS/LVTTL interface levels.
25 Q/2 Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
26 2XQ Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
