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870919BRILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ICS870919BVI REVISION B JANUARY 10, 2012 10 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Schematic Layout
Figure 1 shows an example of 870919I application schematic. In this
example, the device is operated at VDD = AVDD = 3.3V. As with any
high speed analog circuitry, the power supply pins are vulnerable to
random noise. To achieve optimum jitter performance, power supply
isolation is required. The 870919I provides separate power supplies
to isolate any high switching noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side. The other components can be on the opposite side of the
PCB.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set.
Figure 1. 870919I Application Schematic
R4
35
REF_SEL
R5
35
nQ5
VDD
VDD
RU2
Not Install
VDD
nP E
Set Logic
Input to
'1'
Receiver
VDD
muRata, BLM18BB221SN1
FB1
1 2
RD2
1K
3.3V
2XQ
RU1
1K
Zo = 50
F REQ_SEL
Logic Control Input Examples
Q0
LOCK
To Logic
Input
pins
C4
0.1uF
Unused output can be left floating. There
should no trace attached to unused output.
Device characterized with all outputs
terminated.
Q/2
Receiver
AV DD
C7
0.1 uF
Ro ~ 7 O hm
Q1
Driver_LVCMOS
Zo = 50
FEEDBACK
C3
0. 1u F
VDD
Q3
C6
0 . 1uF
QE/nRST
VDD
R1
1-2
Q1
R3
43
Set Logic
Input to
'0'
R6
0
VDD
VDD=3.3V
Zo = 50 Ohm
SYNC0
Q0
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
28
27
26
25
GND
nQ5
VDD
OE/nRST
FEEDBACK
REF_SEL
SY NC0
AVDD
nPE
AGND
SY NC1
FREQ_SEL
GND
Q0 VDD
Q1
GND
PLL_EN
LOCK
GND
Q2
VDD
Q3
GND
Q4
VDD
2XQ
Q/2
C1
1 0uF
2XQ
C8
1 0uF
RD1
Not Install
To Logic
In p u t
pins
R2
35
C5
0. 1u F
C2
0.1uF
Q2
SYNC1 PLL_EN
VDD
VDD
VDD
AGND
ICS870919BVI REVISION B JANUARY 10, 2012 11 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS870919I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS870919I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 0.3V = 3.6V, which gives worst case results.
• Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.6V *5mA = 18mW
• Output Impedance R
OUT
Power Dissipation due to Loading 50 to V
DD
/2
Output Current I
OUT
= V
DD_MAX
/ [2 * (50 + R
OUT
)] = 3.6V / [2 * (50 + 15)] = 27.7mA
• Power Dissipation on the R
OUT
per LVCMOS output
Power (R
OUT
) = R
OUT
* (I
OUT
)
2
= 15 * (27.7mA)
2
= 11.5mW per output
• Total Power (R
OUT
) = R
OUT
(per output) * number of outputs = 11.5mW * 8 outputs = 92mW
Dynamic Power Dissipation for Q = 80MHz
Power (80MHz) = C
PD
* Frequency * (V
DD
)
2
= 240pF * 80MHz * (3.6V)
2
= 249mW
Total Power
= Power (core)
MAX
+ Total Power (R
OUT
) + Power (80MHz)
= 18mW + 92mW + 249mW
= 359mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 66°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.359W * 66°C/W = 108.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
ICS870919BVI REVISION B JANUARY 10, 2012 12 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Table 6. Thermal Resistance
JA
for a 28 Lead QSOP, Forced Convection
JA
by Velocity
Linear Feet per Minute 0200500
Multi-Layer PCB, JEDEC Standard Test Boards 66.0°C/W 58.3°C/W 55.2°C/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

870919BRILF

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Manufacturer:
IDT
Description:
Clock Generators & Support Products 8-OUTPUT LVCMOS CLK GENERATOR
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