ICS870919BVI REVISION B JANUARY 10, 2012 7 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Table 5. AC Electrical Characteristics, V
DD
= AV
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured between coincident rising output edges of Q0:Q4, 2XQ, Q/2 and the falling edge of nQ5.
NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
SYNC[0:1] Input Reference
Frequency
Feedback of Q[0:4] or nQ5,
FREQ_SEL = 0
540MHz
Feedback of Q[0:4] or nQ5,
FREQ_SEL = 1
10 80 MHz
Feedback of 2XQ, FREQ_SEL = 0 10 80 MHz
Feedback of 2XQ or FREQ_SEL = 1 20 100 MHz
Feedback of Q/2, FREQ_SEL = 0 2.5 20 MHz
Feedback of Q/2 or FREQ_SEL = 1 5 40 MHz
f
OUT
Output Frequency
2XQ 160 MHz
Q[0:4], nQ5 80 MHz
Q/2 40 MHz
idc Input Duty Cycle SYNC0, SYNC1 25 75 %
t
R
/ t
F
Input Rise/ Fall Time SYNC0, SYNC1 3 ns
tsk(o)
Output Skew; NOTE 1, 2
Rising edges of Q[0:4]
(incl. Q/2 if nPE = 0)
300 ps
Output Skew; NOTE 1, 2
Falling edges of Q[0:4]
(incl. Q/2 if nPE = 1)
300 ps
Output Skew; NOTE 1, 2, 3
Rising edge of Q[0:4] 2XQ, Q/2 and
Falling edge of nQ5
500 ps
t
PW
Pulse Width
2XQ >40MHz t
PERIOD
/2 - 0.4 t
PERIOD
/2 + 0.4 ns
Q[0:4], nQ5 80MHz t
PERIOD
/2 - 0.4 t
PERIOD
/2 + 0.4 ns
Q/2 40MHz t
PERIOD
/2 - 0.4 t
PERIOD
/2 + 0.4 ns
tjit(cc) Cycle-to-Cycle Jitter
Q[0:4], nQ5 20MHz, FREQ_SEL = 0 165 ps
Q[0:4], nQ5 20MHz, FREQ_SEL = 1 415 ps
t
Static Phase Offset,
(SYNC[0:1] to
FEEDBACK delay);
NOTE 2, 4
Q[0:4], nQ5 80MHz and nPE = 0 -500 1200 ps
Q[0:4], nQ5 80MHz and nPE = 1 -500 500 ps
t
PZL
Output Enable Time;
NOTE 5
OE/nRST Low-to-High 14 ns
t
PHZ
/
t
PLZ
Output Disable
Time; NOTE 5
OE/nRST High-to-Low 14 ns
t
R
/ t
F
Output
Rise/ Fall Time
Q[0:4],
nQ5, 2XQ,
Q/2
0.8V – 2.0V 0.2 2 ns
t
LOCK
PLL Lock Time 10 ms
