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870919BRILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
ICS870919BVI REVISION B JANUARY 10, 2012 4 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Table 2. Pin Characteristics
Device Configuration
The ICS870919I requires a connection of one of the clock outputs to
the FEEDBACK input to close the PLL feedback path. The selection
of the output (output divider) for PLL feedback will impact the device
configuration and input to output frequency ratio and frequency
ranges. See Table 3G for details.
Function Tables
Table 3A. OE/nRST Mode Configuration Table
Table 3B. REF_SEL Mode Configuration Table
Table 3C. nPE Mode Configuration Table
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance (total) V
DD
= AV
DD
= 3.6V 240 pF
R
PULLDOWN
Input Pulldown Resistor nPE 56 k
R
OUT
Output Impedance 15
Input
OperationOE/nRST
0
Device is reset and the outputs Q0:Q4, nQ5, 2XQ, Q/2 are in high-impedance state. This control is asynchronous.
Synchronous output operation requires a reset to the device at start-up by applying logic LOW level.
1 Outputs are enabled.
Input
OperationREF_SEL
0 SYNC0 is the selected PLL reference clock.
1 SYNC1 is the selected PLL reference clock.
Input
OperationnPE
0 The rising edge of the 2XQ, Q0:Q4 and Q/2 outputs and the falling edge of the nQ5 output are synchronized.
1 The falling edge of the 2XQ, Q0:Q4 and Q/2 outputs and the rising edge of the nQ5 output are synchronized.
ICS870919BVI REVISION B JANUARY 10, 2012 5 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Table 3D. FREQ_SEL Mode Configuration Table
Table 3E. PLL_EN Mode Configuration Table
Table 3F. LOCK Mode Configuration Table
Table 3G. Frequency Configuration Table
NOTE 1: The nQ5 output is inverted (180° phase shift) with respect to Q0:Q4.
NOTE 2: The input reference frequency is limited to 100MHz maximum.
Input
OperationFREQ_SEL
0
The VCO output is frequency-divided by 2. This setting allows for a lower input frequency range.
See also table 3G for available frequency ranges.
1
The VCO output is frequency-divided by 1. This setting allows for a higher input frequency range.
See also table 3G for available frequency ranges.
Input
OperationPLL_EN
0
The PLL is bypassed. The selected input reference clock is routed to the output dividers for low-frequency board test
purpose. The PLL-related AC specifications do not apply in PLL bypass mode.
1 The PLL is enabled and locks to the selected input reference signal.
Output
OperationLOCK
0 PLL is not locked to the selected input reference clock.
1 PLL is locked to the selected input reference clock.
Outputs Used for
PLL Feedback FREQ_SEL
Input Frequency Range
(MHz)
Output Frequency Range (MHz) and
Output-to-Input Frequency Multiplication Factor
SYNC[0:1] Q[0:4], nQ5
NOTE1
2XQ Q/2
Q0, Q1, Q2,
Q3, Q4 or nQ5
0 5 - 40 5 - 40 (1x) 10 - 80 (2x) 2.5 - 20 (0.5x)
1 10 - 80 10 - 80 (1x) 20 - 160 (2x) 5 - 40 (0.5x)
2XQ
0 10 - 80 5 - 40 (0.5x) 10 - 80 (1x) 2.5 - 20 (0.25x)
1 20 - 100
NOTE2
10 - 50 (0.5x) 20 - 100 (1x) 5 - 25 (0.25x)
Q/2
0 2.5 - 20 5 - 40 (2x) 10 - 80 (4x) 2.5 - 20 (1x)
1 5 - 40 10 - 80 (2x) 20 - 160 (4x) 5 - 40 (1x)
ICS870919BVI REVISION B JANUARY 10, 2012 6 ©2012 Integrated Device Technology, Inc.
ICS870919I Data Sheet LVCMOS CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= AV
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= AV
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
DD(ABS MAX)
4.6V
Inputs, V
I
-0.5V to V
DD(ABS MAX)
+ 0.5V
Outputs, V
O
-0.5V to V
DD(ABS MAX)
+ 0.5V
Package Thermal Impedance,
JA
28 Lead QSOP
28 Lead PLCC
66.0°C/W (0 lfpm)
46.4°C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD,
AV
DD
Positive Supply Voltage 3.0 3.3 3.6 V
I
DDQ
Quiescent Power Supply Current
V
DD
= AV
DD
= max., OE/nRST = 0,
SYNCx = 0, all outputs open
5mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current
FREQ_SEL,
FEEDBACK,
SYNCn, OE/nRST,
REF_SEL, PLL_EN
V
DD
= V
IN
= 3.3V 5 µA
nPE V
DD
= V
IN
= 3.3V 150 µA
I
IL
Input Low Current
FREQ_SEL,
FEEDBACK, nPE,
SYNCn, OE/nRST,
REF_SEL, PLL_EN
V
DD
= 3.3V, V
IN
= 0V -5 µA
V
OH
Output High Voltage
Q0:Q4, nQ5, 2XQ,
Q/2, LOCK
I
OH
= -24mA 2.6 V
V
OL
Output Low Voltage
Q0:Q4, nQ5, 2XQ,
Q/2, LOCK
I
OL
= 24mA 0.5 V
I
OZ
Output
Leakage Current
Q0:Q4, nQ5,
2XQ, Q/2
OE/nRST = 0,
V
OUT
= 0V or V
DD
,
V
DD
= 3.6V
±5 µA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

870919BRILF

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Clock Generators & Support Products 8-OUTPUT LVCMOS CLK GENERATOR
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