I
DD
Specifications
Table 9: DDR2 I
DD
Specifications and Conditions – 2GB (Die Revision H)
Values are shown for the MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie
(256 Meg x 8) component data sheet
Parameter Symbol
-80E/
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
CDD0
648 603 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL =
CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data pattern is same as I
DD4W
I
CDD1
738 693 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
I
CDD2P
126 126 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
CDD2Q
279 279 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I
CDD2N
315 279 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
CDD3P
243 198 mA
Slow PDN exit
MR[12] = 1
153 153
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
CDD3N
360 333 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
I
CDD4W
1188 1098 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP
=
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
CDD4R
1143 1053 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
I
CDD5
1368 1323 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
I
CDD6
126 126 mA
Operating bank interleave read current: All device banks interleaving reads,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between val-
id commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
I
CDD7
1953 1728 mA
2GB, 4GB (x72, ECC, DR) 244-Pin DDR2 VLP Mini-RDIMM
I
DD
Specifications
PDF: 09005aef83d94997
hvs18c256_512x72pkz.pdf - Rev. E 4/14 EN
11
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