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4. I
2
C Communications
4.1 I
2
C Protocol
4.1.1 Protocol
The I
2
C protocol is based around access to an address table (see Table 5-1 on page 16) and supports multibyte
reads and writes. The maximum clock rate is 100 kHz.
4.1.2 Signals
The I
2
C interface requires two signals to operate:
SDA - Serial Data
SCL - Serial Clock
A third line, CHG
, is used to signal when the device has seen a change in the status byte:
CHG: Open-drain, active low when any capacitive key in the key mask has changed state or any input line has
changed state since the last I
2
C read. After reading the two status bytes, this pin floats (high) again if it is
pulled up with an external resistor. If the status bytes change back to their original state before the host has
read the status bytes (for example, a touch followed by a release), the CHG
line will be held low. In this case,
a read to any memory location will clear the CHG
line.
4.1.3 Clock Stretching
The device has an internal monitor that resets its I
2
C hardware if either I
2
C-compatible line is held low, without the
other line changing, for more than about 14 ms. It is important that no other device on the bus clock stretches for
14 ms, otherwise the monitor will reset the I
2
C hardware and transfers with the chip may be corrupted.
If the device is configured to run in stand-alone mode, the monitor will be turned off.
4.2 I
2
C Address
There is one preset I
2
C address of 0x12. This is not changeable.
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4.3 Data Read/Write
4.3.1 Writing Data to the Device
The sequence of events required to write data to the device is shown next
.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to write to.
5. The device sends an ACK.
6. The host transmits one or more data bytes; each is acknowledged by the device.
7. If the host sends more than one data byte, they are written to consecutive memory addresses.
8. The device automatically increments the target memory address after writing each data byte.
9. After writing the last data byte, the host should send the STOP condition.
Note: the host should not try to write beyond address 255 because this is the limit of the device’s internal memory
address.
4.3.2 Reading Data From the Device
The sequence of events required to read data from the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to read from.
5. The device sends an ACK.
Table 4-1. Description of Write Data Bits
Key Description
S Start condition
SLA+W Slave address plus write bit
A Acknowledge bit
MemAddress Target memory address within device
Data Data to be written
P Stop condition
SLA+W
MemAddress
AAS
Data A
P
Host to Device Device Tx to Host
SLA+W
MemAddress
AAS
S
SLA+R A
A
P
Host to Device Device Tx to Host
P
A
A
Data 1
Data 2
Data n
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6. The host must then send a STOP and a START condition followed by the slave address again but this time
accompanied by the READ bit.
7. The device returns an ACK, followed by a data byte.
8. The host must return either an ACK or NACK.
1. If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each
time a data byte is transmitted, the device automatically increments the internal address. The device
continues to return data bytes until the host responds with a NACK.
2. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition.
9. The device resets the internal address to the location indicated by the memory address sent to it previously.
Therefore, there is no need to send the memory address again when reading from the same location.
4.4 SDA, SCL
The I
2
C bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I
2
C master and
slave devices can only drive these lines low or leave them open. The termination resistors (not shown) pull the line
up to Vdd if no I
2
C-compatible device is pulling it down.
The termination resistors commonly range from 1 k to 10 k
and should be chosen so that the rise times on SDA
and SCL meet the I
2
C specifications (1 µs maximum).
Standalone mode: if I
2
C-compatible communications are not required, then standalone mode can be enabled by
connecting SDA to Vss and SCL to Vdd. See Section 2.3 on page 6 for more information.

AT42QT1060-MMUR

Mfr. #:
Manufacturer:
Microchip Technology
Description:
Capacitive Touch Sensors INTEGRATED-CIRCUIT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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