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AT42QT1060-MMUR

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Appendix A. I
2
C Basics
A.1 Interface Bus
The device communicates with the host over an I
2
C bus. The following sections give an overview of the bus; more
detailed information is available from www.i2C-bus.org. Devices are connected to the I
2
C bus as shown in Figure A-
1. Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I
2
C devices must be open-drain
type. This implements a wired AND function that allows any and all devices to drive the bus, one at a time. A low
level on the bus is generated when a device outputs a zero.
Figure A-1. I
2
C Interface Bus
A.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be
stable when the clock line is high; the only exception to this rule is for generating START and STOP conditions.
Figure A-2. Data Transfer
SDA
SCL
Data Stable Data Stable
Data Change
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AT42QT1060 [DATASHEET]
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A.3 START and STOP Conditions
The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START
condition on the bus, and is terminated when the host issues a STOP condition. Between the START and STOP
conditions, the bus is considered busy. As shown in Figure A-3, START and STOP conditions are signaled by
changing the level of the SDA line when the SCL line is high.
Figure A-3. START and STOP Conditions
A.4 Address Byte Format
All address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit.
If the READ/WRITE bit is set, a read operation is performed, otherwise a write operation is performed. When the
device recognizes that it is being addressed, it will acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An
address byte consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with
that selected with the option jumpers.
Figure A-4. Address Byte Format
SDA
SCL
START STOP
Addr MSB Addr LSB
R/W
ACK
SDA
SCL
START
12 789
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AT42QT1060 [DATASHEET]
9505H–AT42–04/2015
A.5 Data Byte Format
All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data transfer, the host
generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the
reception. An acknowledge (ACK) is signaled by the receiver pulling the SDA line low during the ninth SCL cycle. If
the receiver leaves the SDA line high, a NACK is signaled.
Figure A-5. Data Byte Format
A.6 Combining Address and Data Bytes into a Transmission
A transmission consists of a START condition, an SLA+R/W, one or more data bytes and a STOP condition. The
wired ANDing of the SCL line is used to implement handshaking between the host and the device. The device
extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the
data transmissions.
Note: Each write or read cycle must end with a stop condition. The device may not respond correctly if a cycle is
terminated by a new start condition.
Figure A-6 shows a typical data transmission. Note that several data bytes can be transmitted between the
SLA+R/W and the STOP.
Figure A-6. Byte Transmission
A.7
Data MSB
Data LSB
ACK
Aggregate
SDA
SCL from
Master
12 789
SDA from
Transmitter
SDA from
Receiver
Data Byte
Stop or
Data Byte
Next
SLA+R/W
Data MSB
Data LSB
ACK
12 789
Addr MSB Addr LSB
R/W
ACK
SDA
SCL
START
12 789
SLA+RW Data Byte
STOP
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AT42QT1060-MMUR

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Manufacturer:
Microchip Technology
Description:
Capacitive Touch Sensors INTEGRATED-CIRCUIT
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