AT42QT1060-MMUR Datasheet AT42QT1060-MMUR | P22-P24

AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

5.17 Address 27: Detection Mask

I/O0 – 6 (Detection Mask): these bits control which I/Os that are configured as outputs will be controlled by their

corresponding capacitive key. A 1 means the output n generates an active output when key n is detecting a touch. A

0 means that the output is controlled by the output buffer. See Section 5.24 on page 24 for I/O register precedence

and example usage.

Default: 0x3F (all I/Os are controlled by key status)

5.18 Address 28: Active Level Mask

I/O0 – 6 (Active Level Mask): these bits control the active logic level for the I/Os that are configured as outputs. A 1

means the output generates an active high output, a 0 means that the output is active low. See Section 5.24 for I/O

Default: 0 (all I/Os are active low output)

5.19 Address 29: User Output Buffer

I/O0 – 6 (User Output Buffer): these bits control the output level for the I/Os that are configured as outputs. A 1

means the output generates an active output, a 0 means that the output is inactive. See Section 5.24 on page 24 for

I/O register precedence and example usage.

Default: 0 (all I/Os inactive)

Table 5-17. Detection Mask

Address b7 b6 b5 b4 b3 b2 b1 b0

27 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Table 5-18. Active Level Mask

Address b7 b6 b5 b4 b3 b2 b1 b0

28 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Table 5-19. User Output Buffer

Address b7 b6 b5 b4 b3 b2 b1 b0

29 Reserved I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

5.20 Address 30: Detection Integrator

DETECTION INTEGRATOR: this 8-bit value controls the number of consecutive measurements that must be

confirmed as having passed the key threshold before that key is registered as being in detect. A value of zero should

not be used.

Default: 3

5.21 Address 31: PWM Level

PWM LEVEL: this 8-bit value controls the duty cycle of the PWM output signal. Valid values are between 0...255.

There is a constant level band at either end of the range, so:

 A value of 0...10 gives a 100% low output

 A value of 250...255 gives a 100% high output

Default: 128 (50:50 duty cycle)

5.22 Address 40 – 51: Key Signal

KEY SIGNAL: addresses 40 – 51 allow key signals to be read for each key, starting with key 0. There are two bytes

of data for each key. These are the key’s 16-bit key signals which are accessed as two 8-bit bytes, stored LSB first.

These addresses are read-only.

Table 5-20. Detection Integrator

Address b7 b6 b5 b4 b3 b2 b1 b0

30 MSB DETECTION INTEGRATOR LSB

Table 5-21. PWM Level

Address b7 b6 b5 b4 b3 b2 b1 b0

31 MSB PWM LEVEL LSB

Table 5-22. Key Signal

Address b7 b6 b5 b4 b3 b2 b1 b0

40 LSB OF KEY SIGNAL FOR KEY 0

41 MSB OF KEY SIGNAL FOR KEY 0

42–51 LSB/MSB OF KEY SIGNAL FOR KEYS 1 – 5

AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

5.23 Address 52 – 63: Reference Data

REFERENCE DATA: addresses 52 – 63 allow reference data to be read for each key, starting with key 0. There are

two bytes of data for each key. These are the key’s 16-bit reference data which is accessed as two 8-bit bytes, stored

LSB first. These addresses are read-only.

5.24 Mask Precedence

Table 5-24 gives the order of priority for the settings in the mask inputs/outputs. The settings in the left-most column

have the highest priority, those in the second-left have the next priority, and so on. If two or more settings are

incompatible then the setting in the left-hand column overrides the other. The right-most column, I/O Function,

specifies the expected result.

Note: X = don’t care (can be a 1 or a 0)

Table 5-23. Reference Data

Address b7 b6 b5 b4 b3 b2 b1 b0

52 LSB OF REFERENCE DATA FOR KEY 0

53 MSB OF REFERENCE DATA FOR KEY 0

54 – 63 LSB/MSB OF REFERENCE DATA FOR KEYS 1 – 5

Table 5-24. Input/Output Mask Precedence

I/O Mask

(bit n)

Detection

Mask (bit n)

PWM Mask

(bit n)

Active Level

Mask (bit n)

User Reg

(bit n)

QTouch Key

(channel n)

I/O Function

(I/O n)

0 X X X X X Digital Input

1 0 0 0 0 X Output - Vdd

1 0 0 0 1 X Output - 0 V

1 0 0 1 0 X Output - 0 V

1 0 0 1 1 X Output - Vdd

1 0 1 0 0 X Output - Vdd

1 0 1 0 1 X PWM Output

1 0 1 1 0 X Output - 0 V

1 0 1 1 1 X PWM Output

1 1 0 0 X Untouched Output - Vdd

1 1 0 0 X Touched Output - 0 V

1 1 0 1 X Untouched Output - 0 V

1 1 0 1 X Touched Output - Vdd

1 1 1 0 X Untouched Output - Vdd

1 1 1 0 X Touched PWM Output

1 1 1 1 X Untouched Output - 0 V

1 1 1 1 X Touched PWM Output

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P35

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Capacitive Touch Sensors INTEGRATED-CIRCUIT

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