6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB 10 REVISION H 07/27/16
9DBV0631 DATASHEET
Additive Phase Jitter: 125M (12kHz to 20MHz)
RMS additive jitter: 251fs
REVISION H 07/27/16 11 6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB
9DBV0631 DATASHEET
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Note: Read/Write address is latched on SADR pin.
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O
O
O
O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host)
IDT
T starT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O
O
O
O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB 12 REVISION H 07/27/16
9DBV0631 DATASHEET
SMBus Table: Output Enable Register
1
Byte 0 Name Control Function Type 0 1 Default
Bit 7
DIF OE5 Output Enable RW Low/Low Enabled 1
Bit 6
DIF OE4 Output Enable RW Low/Low Enabled 1
Bit 5
1
Bit 4
DIF OE3 Output Enable RW Low/Low Enabled 1
Bit 3
DIF OE2 Output Enable RW Low/Low Enabled 1
Bit 2
DIF OE1 Output Enable RW Low/Low Enabled 1
Bit 1
1
Bit 0
DIF OE0 Output Enable RW Low/Low Enabled 1
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1 Name Control Function Type 0 1 Default
Bit 7
PLLMODERB1 PLL Mode Readback Bit 1
R
Latch
Bit 6
PLLMODERB0 PLL Mode Readback Bit 0
R
Latch
Bit 5
PLLMODE_SWCNTRL
Enable SW control of PLL
Mode:
RW
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
0
Bit 4
PLLMODE1 PLL Mode Control Bit 1
RW
1
0
Bit 3
PLLMODE0 PLL Mode Control Bit 0
RW
1
0
Bit 2
1
Bit 1
AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1
Bit 0
AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2 Name Control Function Type 0 1 Default
Bit 7
SLEWRATESEL DIF5 Adjust Slew Rate of DIF5 RW Slow setting Fast setting 1
Bit 6
SLEWRATESEL DIF4 Adjust Slew Rate of DIF4 RW Slow setting Fast setting 1
Bit 5
1
Bit 4
SLEWRATESEL DIF3 Adjust Slew Rate of DIF3 RW Slow setting Fast setting 1
Bit 3
SLEWRATESEL DIF2 Adjust Slew Rate of DIF2 RW Slow setting Fast setting 1
Bit 2
SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW Slow setting Fast setting 1
Bit 1
1
Bit 0
SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW Slow setting Fast setting 1
SMBus Table: Frequency Select Control Register
Byte 3 Name Control Function Type 0 1 Default
Bit 7
1
Bit 6
1
Bit 5
FREQ_SEL_EN
Enable SW selection of
frequency
RW
SW frequency
change disabled
SW frequency
change enabled
0
Bit 4
FSEL1 Freq. Select Bit 1
RW
1
0
Bit 3
FSEL0 Freq. Select Bit 0
RW
1
0
Bit 2
1
Bit 1
1
Bit 0
SLEWRATESEL FB Adjust Slew Rate of FB RW Slow setting Fast setting 1
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Byte 4 is Reserved and reads back 'hFF
Reserved
Reserved
Controls Output Amplitude
Reserved
Reserved
Reserved
Reserved
See Frequency Select Table
Reserved
Reserved
Reserved
See PLL Operating Mode Table
See PLL Operating Mode Table

9DBV0631BKLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 6-output 1.8 V PCIe Gen1-2-3 Zero-Delay
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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